UART Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: `18c8953cf1`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	48.030s	10.538ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.630s	16.779us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	16.241us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.210s	247.396us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.810s	31.980us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.310s	93.901us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	16.241us	20	20	100.00
		uart_csr_aliasing	0.810s	31.980us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	5.277m	121.092ms	50	50	100.00
V2	parity	uart_smoke	48.030s	10.538ms	50	50	100.00
		uart_tx_rx	5.277m	121.092ms	50	50	100.00
V2	parity_error	uart_intr	7.146m	254.642ms	48	50	96.00
		uart_rx_parity_err	6.799m	102.485ms	50	50	100.00
V2	watermark	uart_tx_rx	5.277m	121.092ms	50	50	100.00
		uart_intr	7.146m	254.642ms	48	50	96.00
V2	fifo_full	uart_fifo_full	12.203m	236.109ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	8.919m	125.194ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.998m	109.292ms	298	300	99.33
V2	rx_frame_err	uart_intr	7.146m	254.642ms	48	50	96.00
V2	rx_break_err	uart_intr	7.146m	254.642ms	48	50	96.00
V2	rx_timeout	uart_intr	7.146m	254.642ms	48	50	96.00
V2	perf	uart_perf	21.050m	27.064ms	50	50	100.00
V2	sys_loopback	uart_loopback	19.930s	7.495ms	50	50	100.00
V2	line_loopback	uart_loopback	19.930s	7.495ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.998m	121.079ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.740m	71.764ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	31.600s	6.790ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.014m	6.817ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	29.897m	196.706ms	50	50	100.00
V2	stress_all	uart_stress_all	25.851m	378.121ms	50	50	100.00
V2	alert_test	uart_alert_test	0.600s	47.226us	50	50	100.00
V2	intr_test	uart_intr_test	0.670s	14.996us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.850s	155.120us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.850s	155.120us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.630s	16.779us	5	5	100.00
		uart_csr_rw	0.650s	16.241us	20	20	100.00
		uart_csr_aliasing	0.810s	31.980us	5	5	100.00
		uart_same_csr_outstanding	0.790s	29.949us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.630s	16.779us	5	5	100.00
		uart_csr_rw	0.650s	16.241us	20	20	100.00
		uart_csr_aliasing	0.810s	31.980us	5	5	100.00
		uart_same_csr_outstanding	0.790s	29.949us	20	20	100.00
V2		TOTAL			1086	1090	99.63
V2S	tl_intg_err	uart_sec_cm	0.920s	216.825us	5	5	100.00
		uart_tl_intg_err	1.570s	240.648us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.570s	240.648us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	38.186m	67.053ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1315	1320	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.25	99.27	97.95	100.00	--	98.80	100.00	99.50

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:439) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 2 failures:

Test uart_intr has 2 failures.

13.uart_intr.85587164836851440110512808200241873514317263364405638082980843445542195303694
Line 277, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/13.uart_intr/latest/run.log

  UVM_ERROR @ 27338644605 ps: (uart_scoreboard.sv:439) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 27429057093 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxTimeout
  UVM_INFO @ 32051535249 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxOverflow

36.uart_intr.25682038269111227115289239848197025032877599459264500148404287304970522061137
Line 305, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_intr/latest/run.log

  UVM_ERROR @ 42278639796 ps: (uart_scoreboard.sv:439) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 42365367575 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr
  UVM_INFO @ 43234541168 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxTimeout

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test uart_fifo_reset has 2 failures.
  - 125.uart_fifo_reset.88864910539447504494282431067394525461206484476295887608199861937288385004980
    Line 258, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/125.uart_fifo_reset/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 245.uart_fifo_reset.41860836207678266730150400244838631704152235566720318701250484770775985787334
    Line 258, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/245.uart_fifo_reset/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:753) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

42.uart_stress_all_with_rand_reset.98146631292805331908929099912195197024712841703802661495064306186107684530932
Line 860, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 51080855665 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 51080855665 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 8/10
  UVM_INFO @ 51080855665 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/9
  UVM_INFO @ 51080939001 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]