UART Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: `9656691e03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	33.830s	11.099ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.630s	17.711us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	17.046us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.540s	1.650ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.820s	50.665us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.410s	31.407us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	17.046us	20	20	100.00
		uart_csr_aliasing	0.820s	50.665us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.281m	89.990ms	50	50	100.00
V2	parity	uart_smoke	33.830s	11.099ms	50	50	100.00
		uart_tx_rx	3.281m	89.990ms	50	50	100.00
V2	parity_error	uart_intr	8.932m	280.709ms	50	50	100.00
		uart_rx_parity_err	13.957m	227.540ms	50	50	100.00
V2	watermark	uart_tx_rx	3.281m	89.990ms	50	50	100.00
		uart_intr	8.932m	280.709ms	50	50	100.00
V2	fifo_full	uart_fifo_full	5.534m	124.347ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	4.908m	154.357ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	16.754m	252.837ms	300	300	100.00
V2	rx_frame_err	uart_intr	8.932m	280.709ms	50	50	100.00
V2	rx_break_err	uart_intr	8.932m	280.709ms	50	50	100.00
V2	rx_timeout	uart_intr	8.932m	280.709ms	50	50	100.00
V2	perf	uart_perf	17.832m	19.829ms	50	50	100.00
V2	sys_loopback	uart_loopback	31.140s	8.150ms	50	50	100.00
V2	line_loopback	uart_loopback	31.140s	8.150ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.622m	363.600ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.231m	43.691ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	29.400s	6.516ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.099m	7.064ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	19.143m	122.757ms	49	50	98.00
V2	stress_all	uart_stress_all	47.101m	253.890ms	50	50	100.00
V2	alert_test	uart_alert_test	0.650s	56.085us	50	50	100.00
V2	intr_test	uart_intr_test	0.620s	13.520us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.870s	167.659us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.870s	167.659us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.630s	17.711us	5	5	100.00
		uart_csr_rw	0.650s	17.046us	20	20	100.00
		uart_csr_aliasing	0.820s	50.665us	5	5	100.00
		uart_same_csr_outstanding	0.870s	76.276us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.630s	17.711us	5	5	100.00
		uart_csr_rw	0.650s	17.046us	20	20	100.00
		uart_csr_aliasing	0.820s	50.665us	5	5	100.00
		uart_same_csr_outstanding	0.870s	76.276us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	0.850s	577.972us	5	5	100.00
		uart_tl_intg_err	1.330s	190.843us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.330s	190.843us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	28.495m	106.478ms	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1319	1320	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.29	99.27	97.95	100.00	--	98.80	100.00	99.73

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:372) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *

has 1 failures:

Test uart_long_xfer_wo_dly has 1 failures.

45.uart_long_xfer_wo_dly.78247168039790289382827364662759643470139220193052830149189455606089633541853
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/45.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @ 9043761545 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 9054938105 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 9155938913 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 9470764961 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 9885768281 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1