UART Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: 69c572b503

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	35.620s	5.894ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.600s	14.870us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	37.796us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.590s	1.078ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.830s	31.336us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.330s	48.379us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	37.796us	20	20	100.00
		uart_csr_aliasing	0.830s	31.336us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	6.516m	113.941ms	50	50	100.00
V2	parity	uart_smoke	35.620s	5.894ms	50	50	100.00
		uart_tx_rx	6.516m	113.941ms	50	50	100.00
V2	parity_error	uart_intr	9.217m	313.238ms	50	50	100.00
		uart_rx_parity_err	4.790m	195.007ms	50	50	100.00
V2	watermark	uart_tx_rx	6.516m	113.941ms	50	50	100.00
		uart_intr	9.217m	313.238ms	50	50	100.00
V2	fifo_full	uart_fifo_full	5.912m	248.081ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	7.135m	182.798ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.709m	263.699ms	299	300	99.67
V2	rx_frame_err	uart_intr	9.217m	313.238ms	50	50	100.00
V2	rx_break_err	uart_intr	9.217m	313.238ms	50	50	100.00
V2	rx_timeout	uart_intr	9.217m	313.238ms	50	50	100.00
V2	perf	uart_perf	20.381m	22.080ms	50	50	100.00
V2	sys_loopback	uart_loopback	24.680s	12.836ms	50	50	100.00
V2	line_loopback	uart_loopback	24.680s	12.836ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	7.552m	169.955ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.060m	37.316ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	49.270s	12.247ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.070m	6.992ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	22.704m	150.814ms	50	50	100.00
V2	stress_all	uart_stress_all	38.730m	119.220ms	50	50	100.00
V2	alert_test	uart_alert_test	0.580s	43.473us	50	50	100.00
V2	intr_test	uart_intr_test	0.650s	15.691us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.470s	136.414us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.470s	136.414us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.600s	14.870us	5	5	100.00
		uart_csr_rw	0.650s	37.796us	20	20	100.00
		uart_csr_aliasing	0.830s	31.336us	5	5	100.00
		uart_same_csr_outstanding	0.820s	29.541us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.600s	14.870us	5	5	100.00
		uart_csr_rw	0.650s	37.796us	20	20	100.00
		uart_csr_aliasing	0.830s	31.336us	5	5	100.00
		uart_same_csr_outstanding	0.820s	29.541us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	0.920s	256.536us	5	5	100.00
		uart_tl_intg_err	1.400s	170.198us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.400s	170.198us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	36.440m	124.758ms	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1319	1320	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.28	99.27	97.95	100.00	--	98.80	100.00	99.64

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test uart_fifo_reset has 1 failures.

    • 89.uart_fifo_reset.80670822008543019760633849841837512439888468607289841341772050683907801273656
      Line 258, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/89.uart_fifo_reset/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.05.10_04.48.45
• 2024.05.08_03.58.13
• 2024.05.06_05.13.10
• 2024.05.03_05.27.43
• 2024.05.01_04.42.33
• 2024.04.29_08.15.43