UART Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	29.960s	5.967ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	15.203us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	47.294us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.480s	347.670us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.760s	26.529us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.280s	96.594us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	47.294us	20	20	100.00
		uart_csr_aliasing	0.760s	26.529us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.999m	109.559ms	50	50	100.00
V2	parity	uart_smoke	29.960s	5.967ms	50	50	100.00
		uart_tx_rx	3.999m	109.559ms	50	50	100.00
V2	parity_error	uart_intr	12.016m	420.672ms	50	50	100.00
		uart_rx_parity_err	7.173m	222.450ms	50	50	100.00
V2	watermark	uart_tx_rx	3.999m	109.559ms	50	50	100.00
		uart_intr	12.016m	420.672ms	50	50	100.00
V2	fifo_full	uart_fifo_full	9.659m	152.257ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	7.212m	253.013ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	15.314m	104.174ms	300	300	100.00
V2	rx_frame_err	uart_intr	12.016m	420.672ms	50	50	100.00
V2	rx_break_err	uart_intr	12.016m	420.672ms	50	50	100.00
V2	rx_timeout	uart_intr	12.016m	420.672ms	50	50	100.00
V2	perf	uart_perf	26.737m	31.827ms	50	50	100.00
V2	sys_loopback	uart_loopback	22.660s	13.139ms	50	50	100.00
V2	line_loopback	uart_loopback	22.660s	13.139ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.075m	193.870ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.203m	41.134ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	25.310s	7.167ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	54.290s	6.262ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	29.476m	214.316ms	50	50	100.00
V2	stress_all	uart_stress_all	1.161h	387.147ms	50	50	100.00
V2	alert_test	uart_alert_test	0.630s	11.778us	50	50	100.00
V2	intr_test	uart_intr_test	0.660s	16.496us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.410s	67.097us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.410s	67.097us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	15.203us	5	5	100.00
		uart_csr_rw	0.650s	47.294us	20	20	100.00
		uart_csr_aliasing	0.760s	26.529us	5	5	100.00
		uart_same_csr_outstanding	0.810s	32.487us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	15.203us	5	5	100.00
		uart_csr_rw	0.650s	47.294us	20	20	100.00
		uart_csr_aliasing	0.760s	26.529us	5	5	100.00
		uart_same_csr_outstanding	0.810s	32.487us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	0.840s	116.099us	5	5	100.00
		uart_tl_intg_err	1.400s	77.454us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.400s	77.454us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	57.880m	136.006ms	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1320	1320	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	18	100.00
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.24	99.27	97.95	100.00	--	98.80	100.00	99.46

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