UART Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: `349bab6601`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	40.480s	11.069ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	16.135us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.640s	21.182us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.530s	267.538us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.780s	49.248us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.400s	30.518us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	21.182us	20	20	100.00
		uart_csr_aliasing	0.780s	49.248us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	5.729m	134.177ms	50	50	100.00
V2	parity	uart_smoke	40.480s	11.069ms	50	50	100.00
		uart_tx_rx	5.729m	134.177ms	50	50	100.00
V2	parity_error	uart_intr	6.632m	251.019ms	48	50	96.00
		uart_rx_parity_err	3.886m	125.052ms	50	50	100.00
V2	watermark	uart_tx_rx	5.729m	134.177ms	50	50	100.00
		uart_intr	6.632m	251.019ms	48	50	96.00
V2	fifo_full	uart_fifo_full	12.057m	190.800ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	7.511m	132.454ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	10.196m	340.505ms	300	300	100.00
V2	rx_frame_err	uart_intr	6.632m	251.019ms	48	50	96.00
V2	rx_break_err	uart_intr	6.632m	251.019ms	48	50	96.00
V2	rx_timeout	uart_intr	6.632m	251.019ms	48	50	96.00
V2	perf	uart_perf	19.993m	20.470ms	50	50	100.00
V2	sys_loopback	uart_loopback	25.080s	11.727ms	50	50	100.00
V2	line_loopback	uart_loopback	25.080s	11.727ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.150m	281.311ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.137m	47.329ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	41.520s	6.024ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.087m	7.725ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	26.226m	159.749ms	50	50	100.00
V2	stress_all	uart_stress_all	33.880m	511.829ms	50	50	100.00
V2	alert_test	uart_alert_test	0.590s	12.270us	50	50	100.00
V2	intr_test	uart_intr_test	0.650s	103.653us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.600s	279.333us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.600s	279.333us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	16.135us	5	5	100.00
		uart_csr_rw	0.640s	21.182us	20	20	100.00
		uart_csr_aliasing	0.780s	49.248us	5	5	100.00
		uart_same_csr_outstanding	0.820s	113.611us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	16.135us	5	5	100.00
		uart_csr_rw	0.640s	21.182us	20	20	100.00
		uart_csr_aliasing	0.780s	49.248us	5	5	100.00
		uart_same_csr_outstanding	0.820s	113.611us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	0.840s	122.392us	5	5	100.00
		uart_tl_intg_err	1.520s	326.457us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.520s	326.457us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	38.285m	139.209ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1316	1320	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	99.27	97.95	100.00	--	98.80	100.00	99.55

Failure Buckets

UVM_ERROR (uart_intr_vseq.sv:278) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 2 failures:

Test uart_intr has 2 failures.

6.uart_intr.7167854995332584921410681296475834471252908877534864233925243733545796675227
Line 260, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_intr/latest/run.log

  UVM_ERROR @ 3348153871 ps: (uart_intr_vseq.sv:278) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 3481654138 ps: (uart_intr_vseq.sv:278) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 3606987722 ps: (uart_intr_vseq.sv:278) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 3737654650 ps: (uart_intr_vseq.sv:278) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 3863488235 ps: (uart_intr_vseq.sv:278) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])

40.uart_intr.35311152354678872224689943223199544847973700659040024665637693963725659461861
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/40.uart_intr/latest/run.log

  UVM_ERROR @ 2760997361 ps: (uart_intr_vseq.sv:278) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 3164597361 ps: (uart_intr_vseq.sv:278) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 3514797361 ps: (uart_intr_vseq.sv:278) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 4205397361 ps: (uart_intr_vseq.sv:278) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4210797361 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

UVM_ERROR (cip_base_vseq.sv:753) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

77.uart_stress_all_with_rand_reset.25420574190682855931593540890144464800233024548941360460019498964155298851087
Line 307, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4107005579 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4107005579 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 4107067814 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/6
  UVM_INFO @ 4107109749 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

UVM_ERROR (uart_scoreboard.sv:372) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

93.uart_stress_all_with_rand_reset.50308044175596048576268270842202905733855397938323498477864877721462957234362
Line 282, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/93.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10904235802 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_INFO @ 11067648874 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 32/504
  UVM_INFO @ 11541299722 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 33/504
  UVM_ERROR @ 11585241250 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 11945126482 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1