UART Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: `eb776817a5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	38.640s	10.586ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.640s	13.214us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.630s	42.511us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.490s	181.850us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.700s	26.301us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.410s	333.076us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.630s	42.511us	20	20	100.00
		uart_csr_aliasing	0.700s	26.301us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.273m	108.404ms	50	50	100.00
V2	parity	uart_smoke	38.640s	10.586ms	50	50	100.00
		uart_tx_rx	3.273m	108.404ms	50	50	100.00
V2	parity_error	uart_intr	9.588m	383.084ms	50	50	100.00
		uart_rx_parity_err	8.192m	156.076ms	50	50	100.00
V2	watermark	uart_tx_rx	3.273m	108.404ms	50	50	100.00
		uart_intr	9.588m	383.084ms	50	50	100.00
V2	fifo_full	uart_fifo_full	5.776m	143.311ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	13.140m	106.754ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.246m	130.070ms	300	300	100.00
V2	rx_frame_err	uart_intr	9.588m	383.084ms	50	50	100.00
V2	rx_break_err	uart_intr	9.588m	383.084ms	50	50	100.00
V2	rx_timeout	uart_intr	9.588m	383.084ms	50	50	100.00
V2	perf	uart_perf	24.932m	26.828ms	50	50	100.00
V2	sys_loopback	uart_loopback	20.690s	6.251ms	50	50	100.00
V2	line_loopback	uart_loopback	20.690s	6.251ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	11.102m	113.385ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.413m	93.786ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	30.690s	6.991ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.115m	7.119ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	24.098m	169.339ms	50	50	100.00
V2	stress_all	uart_stress_all	38.770m	233.369ms	50	50	100.00
V2	alert_test	uart_alert_test	0.640s	14.322us	50	50	100.00
V2	intr_test	uart_intr_test	0.640s	25.389us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.590s	522.245us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.590s	522.245us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.640s	13.214us	5	5	100.00
		uart_csr_rw	0.630s	42.511us	20	20	100.00
		uart_csr_aliasing	0.700s	26.301us	5	5	100.00
		uart_same_csr_outstanding	0.800s	334.519us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.640s	13.214us	5	5	100.00
		uart_csr_rw	0.630s	42.511us	20	20	100.00
		uart_csr_aliasing	0.700s	26.301us	5	5	100.00
		uart_same_csr_outstanding	0.800s	334.519us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	0.960s	499.835us	5	5	100.00
		uart_tl_intg_err	1.430s	205.495us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.430s	205.495us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	31.530m	249.729ms	97	100	97.00
V3		TOTAL			97	100	97.00
		TOTAL			1317	1320	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	18	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.27	99.27	97.95	100.00	--	98.80	100.00	99.59

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:753) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

54.uart_stress_all_with_rand_reset.74083442195216224123285466286820008612143027723543846796206704819965293665395
Line 435, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/54.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13000740829 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 13000740829 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 5/5
  UVM_INFO @ 13000774858 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_smoke_vseq] finished run 1/2
  UVM_INFO @ 13000813748 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

91.uart_stress_all_with_rand_reset.22277839378437819365066079004744991665673840877842779861533001790422363140686
Line 331, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 23503280814 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 23503280814 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 3/10
  UVM_INFO @ 23503364148 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 3/10

UVM_ERROR (uart_scoreboard.sv:372) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

25.uart_stress_all_with_rand_reset.50561036026990641461817514670953182422220527806684112216207870198094573940588
Line 508, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 84220271457 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_INFO @ 84234492074 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_smoke_vseq] finished run 2/2
  UVM_INFO @ 84273154233 ps: (uart_stress_all_vseq.sv:53) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_stress_all_vseq] starting stress_all sub-sequence uart_rx_parity_err_vseq
  UVM_INFO @ 84583744953 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/433
  UVM_INFO @ 85096043169 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/433