UART Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: be3d980075

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	25.980s	6.216ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.630s	16.160us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.660s	25.556us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.620s	676.514us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.770s	63.396us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.370s	109.481us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.660s	25.556us	20	20	100.00
		uart_csr_aliasing	0.770s	63.396us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.528m	103.523ms	50	50	100.00
V2	parity	uart_smoke	25.980s	6.216ms	50	50	100.00
		uart_tx_rx	4.528m	103.523ms	50	50	100.00
V2	parity_error	uart_intr	10.808m	386.638ms	50	50	100.00
		uart_rx_parity_err	5.346m	144.986ms	50	50	100.00
V2	watermark	uart_tx_rx	4.528m	103.523ms	50	50	100.00
		uart_intr	10.808m	386.638ms	50	50	100.00
V2	fifo_full	uart_fifo_full	17.824m	270.359ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	7.271m	234.189ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.961m	136.878ms	300	300	100.00
V2	rx_frame_err	uart_intr	10.808m	386.638ms	50	50	100.00
V2	rx_break_err	uart_intr	10.808m	386.638ms	50	50	100.00
V2	rx_timeout	uart_intr	10.808m	386.638ms	50	50	100.00
V2	perf	uart_perf	28.619m	33.232ms	50	50	100.00
V2	sys_loopback	uart_loopback	23.940s	7.885ms	50	50	100.00
V2	line_loopback	uart_loopback	23.940s	7.885ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	6.337m	106.075ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.759m	67.161ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	34.060s	6.068ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.120m	7.735ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	18.247m	112.635ms	50	50	100.00
V2	stress_all	uart_stress_all	29.037m	176.018ms	50	50	100.00
V2	alert_test	uart_alert_test	0.600s	13.032us	50	50	100.00
V2	intr_test	uart_intr_test	0.620s	89.270us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.740s	1.477ms	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.740s	1.477ms	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.630s	16.160us	5	5	100.00
		uart_csr_rw	0.660s	25.556us	20	20	100.00
		uart_csr_aliasing	0.770s	63.396us	5	5	100.00
		uart_same_csr_outstanding	0.810s	107.753us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.630s	16.160us	5	5	100.00
		uart_csr_rw	0.660s	25.556us	20	20	100.00
		uart_csr_aliasing	0.770s	63.396us	5	5	100.00
		uart_same_csr_outstanding	0.810s	107.753us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	0.920s	344.361us	5	5	100.00
		uart_tl_intg_err	1.370s	523.369us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.370s	523.369us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	32.739m	145.371ms	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1320	1320	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	18	100.00
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.28	99.27	97.95	100.00	--	98.80	100.00	99.68

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