UART Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: `1579f6a912`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	25.180s	5.682ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.650s	55.452us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.670s	28.125us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.640s	463.536us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.810s	33.876us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.500s	117.711us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.670s	28.125us	20	20	100.00
		uart_csr_aliasing	0.810s	33.876us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.956m	122.793ms	50	50	100.00
V2	parity	uart_smoke	25.180s	5.682ms	50	50	100.00
		uart_tx_rx	3.956m	122.793ms	50	50	100.00
V2	parity_error	uart_intr	18.021m	687.638ms	50	50	100.00
		uart_rx_parity_err	6.945m	236.348ms	50	50	100.00
V2	watermark	uart_tx_rx	3.956m	122.793ms	50	50	100.00
		uart_intr	18.021m	687.638ms	50	50	100.00
V2	fifo_full	uart_fifo_full	6.508m	187.409ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	8.467m	205.341ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.818m	206.598ms	300	300	100.00
V2	rx_frame_err	uart_intr	18.021m	687.638ms	50	50	100.00
V2	rx_break_err	uart_intr	18.021m	687.638ms	50	50	100.00
V2	rx_timeout	uart_intr	18.021m	687.638ms	50	50	100.00
V2	perf	uart_perf	30.575m	32.666ms	50	50	100.00
V2	sys_loopback	uart_loopback	21.250s	12.275ms	50	50	100.00
V2	line_loopback	uart_loopback	21.250s	12.275ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.956m	56.378ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.804m	74.143ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	42.220s	6.866ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.064m	6.974ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	25.430m	204.174ms	50	50	100.00
V2	stress_all	uart_stress_all	26.867m	215.413ms	50	50	100.00
V2	alert_test	uart_alert_test	0.660s	11.994us	50	50	100.00
V2	intr_test	uart_intr_test	0.640s	63.397us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.320s	559.589us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.320s	559.589us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.650s	55.452us	5	5	100.00
		uart_csr_rw	0.670s	28.125us	20	20	100.00
		uart_csr_aliasing	0.810s	33.876us	5	5	100.00
		uart_same_csr_outstanding	0.790s	31.955us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.650s	55.452us	5	5	100.00
		uart_csr_rw	0.670s	28.125us	20	20	100.00
		uart_csr_aliasing	0.810s	33.876us	5	5	100.00
		uart_same_csr_outstanding	0.790s	31.955us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	0.940s	136.335us	5	5	100.00
		uart_tl_intg_err	1.420s	85.571us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.420s	85.571us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	36.902m	108.676ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1319	1320	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	18	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.29	99.27	97.95	100.00	--	98.80	100.00	99.71

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:753) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.

has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

18.uart_stress_all_with_rand_reset.13092530641974846499556409695548785160732422866409888122595944592801561974105
Line 254, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 359146380 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 359146380 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 359146380 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/5
  UVM_INFO @ 359237289 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]