UART Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: `2cf28c40e5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	36.660s	5.841ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.630s	53.832us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.680s	19.384us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.440s	674.024us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.840s	28.348us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.480s	153.971us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.680s	19.384us	20	20	100.00
		uart_csr_aliasing	0.840s	28.348us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	5.692m	146.950ms	50	50	100.00
V2	parity	uart_smoke	36.660s	5.841ms	50	50	100.00
		uart_tx_rx	5.692m	146.950ms	50	50	100.00
V2	parity_error	uart_intr	8.708m	228.762ms	50	50	100.00
		uart_rx_parity_err	3.657m	128.522ms	50	50	100.00
V2	watermark	uart_tx_rx	5.692m	146.950ms	50	50	100.00
		uart_intr	8.708m	228.762ms	50	50	100.00
V2	fifo_full	uart_fifo_full	10.462m	328.441ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	4.420m	205.674ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	15.572m	108.408ms	300	300	100.00
V2	rx_frame_err	uart_intr	8.708m	228.762ms	50	50	100.00
V2	rx_break_err	uart_intr	8.708m	228.762ms	50	50	100.00
V2	rx_timeout	uart_intr	8.708m	228.762ms	50	50	100.00
V2	perf	uart_perf	21.237m	21.510ms	50	50	100.00
V2	sys_loopback	uart_loopback	27.030s	10.146ms	50	50	100.00
V2	line_loopback	uart_loopback	27.030s	10.146ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	7.276m	174.413ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.916m	76.708ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	42.150s	12.478ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.073m	7.606ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	19.983m	188.667ms	49	50	98.00
V2	stress_all	uart_stress_all	24.648m	572.491ms	50	50	100.00
V2	alert_test	uart_alert_test	0.630s	12.091us	50	50	100.00
V2	intr_test	uart_intr_test	0.650s	11.815us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.340s	113.593us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.340s	113.593us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.630s	53.832us	5	5	100.00
		uart_csr_rw	0.680s	19.384us	20	20	100.00
		uart_csr_aliasing	0.840s	28.348us	5	5	100.00
		uart_same_csr_outstanding	0.770s	125.123us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.630s	53.832us	5	5	100.00
		uart_csr_rw	0.680s	19.384us	20	20	100.00
		uart_csr_aliasing	0.840s	28.348us	5	5	100.00
		uart_same_csr_outstanding	0.770s	125.123us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	0.890s	62.877us	5	5	100.00
		uart_tl_intg_err	1.500s	182.223us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.500s	182.223us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	37.492m	335.998ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1316	1320	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.28	99.27	97.95	100.00	--	98.80	100.00	99.66

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:439) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxWatermark has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

6.uart_stress_all_with_rand_reset.87204650297644141640674562363125269298918627370533307347586687515327923753085
Line 1195, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 216987040258 ps: (uart_scoreboard.sv:439) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 217037600258 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxParityErr
  UVM_INFO @ 217049760258 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 89/446
  UVM_INFO @ 217105360258 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

16.uart_stress_all_with_rand_reset.103941501482380449505425630458792507044356651265967703590834833020981174149283
Line 259, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 267152480 ps: (uart_scoreboard.sv:439) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 291793846 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/259
  UVM_INFO @ 312645852 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr
  UVM_INFO @ 318982504 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/259

UVM_ERROR (uart_scoreboard.sv:372) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

Test uart_long_xfer_wo_dly has 1 failures.

13.uart_long_xfer_wo_dly.72864373941637095260313294009716733207368344668185390134142650588291930671532
Line 254, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/13.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @ 113319207028 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 113623091812 ps: (uart_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_ERROR @ 114106742740 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 114590746612 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 114894807868 ps: (uart_scoreboard.sv:372) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_noise_filter has 1 failures.
  - 14.uart_noise_filter.80987229760435354312117561007355316110250394604391673473440158721161535462343
    Line 268, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/14.uart_noise_filter/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```