UART Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: `0e5093d709`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	38.130s	5.464ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.600s	15.828us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.660s	14.457us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.590s	455.001us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.790s	27.999us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.450s	61.061us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.660s	14.457us	20	20	100.00
		uart_csr_aliasing	0.790s	27.999us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	2.737m	75.268ms	50	50	100.00
V2	parity	uart_smoke	38.130s	5.464ms	50	50	100.00
		uart_tx_rx	2.737m	75.268ms	50	50	100.00
V2	parity_error	uart_intr	6.185m	337.294ms	50	50	100.00
		uart_rx_parity_err	6.292m	95.908ms	50	50	100.00
V2	watermark	uart_tx_rx	2.737m	75.268ms	50	50	100.00
		uart_intr	6.185m	337.294ms	50	50	100.00
V2	fifo_full	uart_fifo_full	7.625m	142.749ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	9.683m	226.107ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.487m	102.056ms	300	300	100.00
V2	rx_frame_err	uart_intr	6.185m	337.294ms	50	50	100.00
V2	rx_break_err	uart_intr	6.185m	337.294ms	50	50	100.00
V2	rx_timeout	uart_intr	6.185m	337.294ms	50	50	100.00
V2	perf	uart_perf	28.698m	30.500ms	50	50	100.00
V2	sys_loopback	uart_loopback	22.310s	10.281ms	50	50	100.00
V2	line_loopback	uart_loopback	22.310s	10.281ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.665m	141.337ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.429m	53.085ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	32.550s	6.703ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	59.990s	6.348ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	24.110m	133.115ms	50	50	100.00
V2	stress_all	uart_stress_all	25.937m	431.518ms	50	50	100.00
V2	alert_test	uart_alert_test	0.630s	47.912us	50	50	100.00
V2	intr_test	uart_intr_test	0.610s	31.399us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.690s	133.057us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.690s	133.057us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.600s	15.828us	5	5	100.00
		uart_csr_rw	0.660s	14.457us	20	20	100.00
		uart_csr_aliasing	0.790s	27.999us	5	5	100.00
		uart_same_csr_outstanding	0.790s	27.846us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.600s	15.828us	5	5	100.00
		uart_csr_rw	0.660s	14.457us	20	20	100.00
		uart_csr_aliasing	0.790s	27.999us	5	5	100.00
		uart_same_csr_outstanding	0.790s	27.846us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	0.890s	69.178us	5	5	100.00
		uart_tl_intg_err	1.490s	1.392ms	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.490s	1.392ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	37.053m	439.573ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1319	1320	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	18	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.28	99.27	97.95	100.00	--	98.80	100.00	99.64

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:753) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.

has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

6.uart_stress_all_with_rand_reset.69389927832065169855317191674322618223931693747023522826484317475128174003395
Line 634, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 48213925136 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 48213925136 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 8/10
  UVM_INFO @ 48213985136 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 8/10