UART Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: `edf2fd5092`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	45.180s	6.242ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.680s	53.156us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.690s	40.720us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.690s	958.671us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.820s	35.771us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.100s	67.192us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.690s	40.720us	20	20	100.00
		uart_csr_aliasing	0.820s	35.771us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.930m	118.224ms	50	50	100.00
V2	parity	uart_smoke	45.180s	6.242ms	50	50	100.00
		uart_tx_rx	3.930m	118.224ms	50	50	100.00
V2	parity_error	uart_intr	11.258m	279.634ms	50	50	100.00
		uart_rx_parity_err	7.513m	195.733ms	50	50	100.00
V2	watermark	uart_tx_rx	3.930m	118.224ms	50	50	100.00
		uart_intr	11.258m	279.634ms	50	50	100.00
V2	fifo_full	uart_fifo_full	5.121m	127.566ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.961m	144.141ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.766m	165.444ms	300	300	100.00
V2	rx_frame_err	uart_intr	11.258m	279.634ms	50	50	100.00
V2	rx_break_err	uart_intr	11.258m	279.634ms	50	50	100.00
V2	rx_timeout	uart_intr	11.258m	279.634ms	50	50	100.00
V2	perf	uart_perf	20.240m	26.972ms	50	50	100.00
V2	sys_loopback	uart_loopback	22.320s	6.622ms	50	50	100.00
V2	line_loopback	uart_loopback	22.320s	6.622ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.531m	85.829ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.228m	73.055ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	37.340s	6.860ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.119m	7.207ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	19.913m	152.450ms	50	50	100.00
V2	stress_all	uart_stress_all	39.246m	553.327ms	49	50	98.00
V2	alert_test	uart_alert_test	0.610s	11.975us	50	50	100.00
V2	intr_test	uart_intr_test	0.680s	41.423us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.500s	471.483us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.500s	471.483us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.680s	53.156us	5	5	100.00
		uart_csr_rw	0.690s	40.720us	20	20	100.00
		uart_csr_aliasing	0.820s	35.771us	5	5	100.00
		uart_same_csr_outstanding	0.810s	33.924us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.680s	53.156us	5	5	100.00
		uart_csr_rw	0.690s	40.720us	20	20	100.00
		uart_csr_aliasing	0.820s	35.771us	5	5	100.00
		uart_same_csr_outstanding	0.810s	33.924us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	0.870s	448.061us	5	5	100.00
		uart_tl_intg_err	1.400s	86.943us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.400s	86.943us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	31.608m	659.429ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1318	1320	99.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.57

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty

has 2 failures:

Test uart_stress_all has 1 failures.

3.uart_stress_all.81669297906639388127145322700877770676270661046411467977426546596088798331721
Line 333, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/3.uart_stress_all/latest/run.log

  UVM_ERROR @ 201899302166 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 201946848096 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxParityErr
  UVM_INFO @ 201995348581 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxDone

Test uart_stress_all_with_rand_reset has 1 failures.

73.uart_stress_all_with_rand_reset.6095719053508715949730001944620682471311202324114421978514851775402365796919
Line 552, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/73.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 36283566916 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 36359137740 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/340
  UVM_INFO @ 36464340980 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 8/340
  UVM_INFO @ 36563421820 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 9/340
  UVM_INFO @ 36663359796 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 10/340