UART Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: `5967df933a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	22.610s	10.545ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.640s	15.951us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.710s	20.376us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.550s	750.241us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.920s	52.142us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.320s	46.782us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.710s	20.376us	20	20	100.00
		uart_csr_aliasing	0.920s	52.142us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	6.243m	121.235ms	50	50	100.00
V2	parity	uart_smoke	22.610s	10.545ms	50	50	100.00
		uart_tx_rx	6.243m	121.235ms	50	50	100.00
V2	parity_error	uart_intr	9.875m	402.500ms	48	50	96.00
		uart_rx_parity_err	7.548m	140.594ms	50	50	100.00
V2	watermark	uart_tx_rx	6.243m	121.235ms	50	50	100.00
		uart_intr	9.875m	402.500ms	48	50	96.00
V2	fifo_full	uart_fifo_full	7.932m	145.130ms	49	50	98.00
V2	fifo_overflow	uart_fifo_overflow	6.525m	237.280ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	11.013m	118.707ms	299	300	99.67
V2	rx_frame_err	uart_intr	9.875m	402.500ms	48	50	96.00
V2	rx_break_err	uart_intr	9.875m	402.500ms	48	50	96.00
V2	rx_timeout	uart_intr	9.875m	402.500ms	48	50	96.00
V2	perf	uart_perf	27.575m	36.792ms	50	50	100.00
V2	sys_loopback	uart_loopback	21.030s	8.535ms	50	50	100.00
V2	line_loopback	uart_loopback	21.030s	8.535ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.398m	162.318ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.319m	88.861ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	44.750s	12.247ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.168m	7.706ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	24.991m	139.869ms	50	50	100.00
V2	stress_all	uart_stress_all	42.505m	504.340ms	50	50	100.00
V2	alert_test	uart_alert_test	0.620s	39.378us	50	50	100.00
V2	intr_test	uart_intr_test	0.730s	31.486us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.560s	123.375us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.560s	123.375us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.640s	15.951us	5	5	100.00
		uart_csr_rw	0.710s	20.376us	20	20	100.00
		uart_csr_aliasing	0.920s	52.142us	5	5	100.00
		uart_same_csr_outstanding	0.880s	55.377us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.640s	15.951us	5	5	100.00
		uart_csr_rw	0.710s	20.376us	20	20	100.00
		uart_csr_aliasing	0.920s	52.142us	5	5	100.00
		uart_same_csr_outstanding	0.880s	55.377us	20	20	100.00
V2		TOTAL			1086	1090	99.63
V2S	tl_intg_err	uart_sec_cm	0.800s	121.802us	5	5	100.00
		uart_tl_intg_err	1.410s	74.343us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.410s	74.343us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	30.478m	215.341ms	95	100	95.00
V3		TOTAL			95	100	95.00
		TOTAL			1311	1320	99.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	15	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.57

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 5 failures:

Test uart_intr has 2 failures.

3.uart_intr.9192766866678915142105104203426474238336631404379274590895954841069873020382
Line 258, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/3.uart_intr/latest/run.log

  UVM_ERROR @ 3444489062 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 3491369062 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxWatermark
  UVM_INFO @ 3635769062 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr

26.uart_intr.93003225987019608697879397491141702034309799963813728135080317498686454075809
Line 281, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/26.uart_intr/latest/run.log

  UVM_ERROR @ 112117968583 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 113285500059 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr
  UVM_INFO @ 115578236819 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty

Test uart_stress_all_with_rand_reset has 2 failures.

31.uart_stress_all_with_rand_reset.109235466326581663007993107815093874870096603843443672624177865197824067268727
Line 1159, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 364845571417 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 364845571417 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 365213657695 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/758
  UVM_INFO @ 365444367874 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/758
  UVM_INFO @ 365610202534 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/758

98.uart_stress_all_with_rand_reset.79294096306229063923032907014421968411445735761726448875357498426805590756250
Line 1028, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 106894888433 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 106894888433 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 106940866418 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxDone
  UVM_INFO @ 107331559726 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

Test uart_fifo_reset has 1 failures.

98.uart_fifo_reset.115669399851875032930597766858553044864752365032177158081993285041905324791184
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/98.uart_fifo_reset/latest/run.log

  UVM_ERROR @ 14973333023 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 19976111631 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/5
  UVM_INFO @ 20283035411 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 5/5
  UVM_INFO @ 24698241709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (uart_intr_vseq.sv:312) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

7.uart_stress_all_with_rand_reset.27693500449307435428108042232090540290857390367261349380238300360305316903302
Line 681, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 370447207942 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 370447207942 ps: (uart_intr_vseq.sv:314) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 1df
  UVM_INFO @ 371367984799 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 33/404
  UVM_ERROR @ 371762317738 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 371762317738 ps: (uart_intr_vseq.sv:314) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 1df

20.uart_stress_all_with_rand_reset.72613352934591062431596179109507794155739336543000277188507271674407704419752
Line 315, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 32269124169 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 32269124169 ps: (uart_intr_vseq.sv:314) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 1d5
  UVM_ERROR @ 32765458495 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 32765458495 ps: (uart_intr_vseq.sv:314) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 1d5
  UVM_ERROR @ 33251459467 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_fifo_full has 1 failures.
  - 29.uart_fifo_full.81732846932442036473989270975680530866559407107585817458330583102829441760855
    Line 258, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/29.uart_fifo_full/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:749) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

41.uart_stress_all_with_rand_reset.61942205740112455519282181491911221846384997225453922476150381542745226235855
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  32214817 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  32214817 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @  32345251 ps: (cip_base_vseq.sv:760) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 1/5