UART Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: `d51405297e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	43.550s	6.023ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.700s	37.324us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	64.840us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.550s	901.689us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.820s	30.621us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.330s	48.266us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	64.840us	20	20	100.00
		uart_csr_aliasing	0.820s	30.621us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	7.351m	97.412ms	50	50	100.00
V2	parity	uart_smoke	43.550s	6.023ms	50	50	100.00
		uart_tx_rx	7.351m	97.412ms	50	50	100.00
V2	parity_error	uart_intr	11.035m	415.123ms	49	50	98.00
		uart_rx_parity_err	7.282m	163.423ms	50	50	100.00
V2	watermark	uart_tx_rx	7.351m	97.412ms	50	50	100.00
		uart_intr	11.035m	415.123ms	49	50	98.00
V2	fifo_full	uart_fifo_full	13.144m	143.260ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.119m	204.682ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.027m	201.187ms	300	300	100.00
V2	rx_frame_err	uart_intr	11.035m	415.123ms	49	50	98.00
V2	rx_break_err	uart_intr	11.035m	415.123ms	49	50	98.00
V2	rx_timeout	uart_intr	11.035m	415.123ms	49	50	98.00
V2	perf	uart_perf	25.764m	27.641ms	50	50	100.00
V2	sys_loopback	uart_loopback	20.050s	8.600ms	50	50	100.00
V2	line_loopback	uart_loopback	20.050s	8.600ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	7.445m	125.605ms	47	50	94.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.847m	71.680ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	52.730s	6.485ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.138m	7.272ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	20.726m	122.422ms	50	50	100.00
V2	stress_all	uart_stress_all	28.791m	261.900ms	49	50	98.00
V2	alert_test	uart_alert_test	0.630s	10.742us	50	50	100.00
V2	intr_test	uart_intr_test	0.640s	12.755us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.380s	144.601us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.380s	144.601us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.700s	37.324us	5	5	100.00
		uart_csr_rw	0.650s	64.840us	20	20	100.00
		uart_csr_aliasing	0.820s	30.621us	5	5	100.00
		uart_same_csr_outstanding	0.800s	130.352us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.700s	37.324us	5	5	100.00
		uart_csr_rw	0.650s	64.840us	20	20	100.00
		uart_csr_aliasing	0.820s	30.621us	5	5	100.00
		uart_same_csr_outstanding	0.800s	130.352us	20	20	100.00
V2		TOTAL			1085	1090	99.54
V2S	tl_intg_err	uart_sec_cm	0.870s	88.983us	5	5	100.00
		uart_tl_intg_err	1.370s	213.360us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.370s	213.360us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	31.641m	2.355s	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1313	1320	99.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	15	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.59

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test uart_noise_filter has 3 failures.
  - 16.uart_noise_filter.98327548514541080533430387932873355674289232031775745629218497934632417040958
    Line 262, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/16.uart_noise_filter/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.uart_noise_filter.79662159003569626359476770404320508723909865988249231306928079363332030082387
    Line 263, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_noise_filter/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 2 failures:

Test uart_stress_all has 1 failures.

5.uart_stress_all.43994546506279716009649266707297016346434225518696886228108328124003089924290
Line 280, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/5.uart_stress_all/latest/run.log

  UVM_ERROR @ 32319077579 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 32405855270 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxOverflow
  UVM_INFO @ 38049334475 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxWatermark

Test uart_intr has 1 failures.

9.uart_intr.30996225243702403269048333100875380032287957288846609235392325481804500105066
Line 311, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/9.uart_intr/latest/run.log

  UVM_ERROR @ 51917925090 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 51995988504 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark
  UVM_INFO @ 52152274062 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxDone

UVM_ERROR (uart_intr_vseq.sv:312) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

47.uart_stress_all_with_rand_reset.99030635067353359265592940984673561181056899835225158065366359393012773406275
Line 545, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 247616095226 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 248212470226 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 248589845226 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 24/135
  UVM_ERROR @ 248823345226 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 249401595226 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])

UVM_ERROR (cip_base_vseq.sv:749) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

71.uart_stress_all_with_rand_reset.37097252515469009634258726035158781478342587109031770981503638879156869391931
Line 862, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/71.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 73821501304 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 73821501304 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 5/10
  UVM_INFO @ 73821541175 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_smoke_vseq] finished run 1/2
  UVM_INFO @ 73821595057 ps: (cip_base_vseq.sv:760) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]