UART Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: `c04cc5d074`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	33.380s	5.554ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.610s	181.214us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.660s	18.389us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.760s	408.526us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.820s	26.556us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.520s	113.790us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.660s	18.389us	20	20	100.00
		uart_csr_aliasing	0.820s	26.556us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.999m	122.021ms	50	50	100.00
V2	parity	uart_smoke	33.380s	5.554ms	50	50	100.00
		uart_tx_rx	3.999m	122.021ms	50	50	100.00
V2	parity_error	uart_intr	8.517m	347.951ms	50	50	100.00
		uart_rx_parity_err	4.520m	163.903ms	50	50	100.00
V2	watermark	uart_tx_rx	3.999m	122.021ms	50	50	100.00
		uart_intr	8.517m	347.951ms	50	50	100.00
V2	fifo_full	uart_fifo_full	6.928m	210.651ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	4.591m	209.156ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.114m	199.392ms	299	300	99.67
V2	rx_frame_err	uart_intr	8.517m	347.951ms	50	50	100.00
V2	rx_break_err	uart_intr	8.517m	347.951ms	50	50	100.00
V2	rx_timeout	uart_intr	8.517m	347.951ms	50	50	100.00
V2	perf	uart_perf	26.848m	29.958ms	50	50	100.00
V2	sys_loopback	uart_loopback	21.570s	11.749ms	50	50	100.00
V2	line_loopback	uart_loopback	21.570s	11.749ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.766m	215.689ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.293m	45.964ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	21.210s	12.423ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.104m	6.853ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	19.087m	139.203ms	50	50	100.00
V2	stress_all	uart_stress_all	23.497m	353.308ms	50	50	100.00
V2	alert_test	uart_alert_test	0.650s	41.427us	50	50	100.00
V2	intr_test	uart_intr_test	0.650s	14.155us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.540s	123.193us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.540s	123.193us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.610s	181.214us	5	5	100.00
		uart_csr_rw	0.660s	18.389us	20	20	100.00
		uart_csr_aliasing	0.820s	26.556us	5	5	100.00
		uart_same_csr_outstanding	0.820s	32.721us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.610s	181.214us	5	5	100.00
		uart_csr_rw	0.660s	18.389us	20	20	100.00
		uart_csr_aliasing	0.820s	26.556us	5	5	100.00
		uart_same_csr_outstanding	0.820s	32.721us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	0.830s	56.305us	5	5	100.00
		uart_tl_intg_err	1.500s	555.716us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.500s	555.716us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	35.428m	169.757ms	97	100	97.00
V3		TOTAL			97	100	97.00
		TOTAL			1316	1320	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.59

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

17.uart_stress_all_with_rand_reset.19752620397051224220879749080306701649578022472684906815959951806994680970542
Line 1104, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 192389944983 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 192828664983 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/543
  UVM_INFO @ 193026144983 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/543
  UVM_INFO @ 193297144983 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/543
  UVM_INFO @ 193763224983 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/543

75.uart_stress_all_with_rand_reset.88409279811796294638654255602371156872811501237918869703404366423249159514488
Line 698, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 28572463308 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 28596188912 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 252/933
  UVM_INFO @ 28618451402 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty
  UVM_INFO @ 28705259324 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

UVM_ERROR (cip_base_vseq.sv:749) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

78.uart_stress_all_with_rand_reset.76087712831940265769268737792161341858689936261615614022267657945377715507303
Line 390, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15560670480 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 15560670480 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 4/5
  UVM_INFO @ 15560741377 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_smoke_vseq] finished run 1/2
  UVM_INFO @ 15560824328 ps: (cip_base_vseq.sv:760) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_fifo_reset has 1 failures.
  - 190.uart_fifo_reset.3444948109068259454645935459409539472588155096205408431919080407272542244693
    Line 257, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/190.uart_fifo_reset/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```