UART Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: `a04e34f557`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	38.860s	6.071ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.660s	48.437us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.680s	15.580us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.320s	112.095us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.930s	27.035us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.310s	98.983us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.680s	15.580us	20	20	100.00
		uart_csr_aliasing	0.930s	27.035us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.602m	87.907ms	50	50	100.00
V2	parity	uart_smoke	38.860s	6.071ms	50	50	100.00
		uart_tx_rx	3.602m	87.907ms	50	50	100.00
V2	parity_error	uart_intr	8.394m	311.501ms	49	50	98.00
		uart_rx_parity_err	10.182m	173.260ms	50	50	100.00
V2	watermark	uart_tx_rx	3.602m	87.907ms	50	50	100.00
		uart_intr	8.394m	311.501ms	49	50	98.00
V2	fifo_full	uart_fifo_full	10.673m	276.292ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.249m	231.064ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	6.056m	192.268ms	300	300	100.00
V2	rx_frame_err	uart_intr	8.394m	311.501ms	49	50	98.00
V2	rx_break_err	uart_intr	8.394m	311.501ms	49	50	98.00
V2	rx_timeout	uart_intr	8.394m	311.501ms	49	50	98.00
V2	perf	uart_perf	26.413m	31.149ms	50	50	100.00
V2	sys_loopback	uart_loopback	22.390s	10.251ms	50	50	100.00
V2	line_loopback	uart_loopback	22.390s	10.251ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.476m	140.367ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.214m	55.902ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	44.150s	6.440ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.001m	8.159ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	23.054m	120.937ms	50	50	100.00
V2	stress_all	uart_stress_all	48.029m	444.456ms	50	50	100.00
V2	alert_test	uart_alert_test	0.610s	28.768us	50	50	100.00
V2	intr_test	uart_intr_test	0.650s	46.489us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.540s	220.348us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.540s	220.348us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.660s	48.437us	5	5	100.00
		uart_csr_rw	0.680s	15.580us	20	20	100.00
		uart_csr_aliasing	0.930s	27.035us	5	5	100.00
		uart_same_csr_outstanding	0.820s	32.261us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.660s	48.437us	5	5	100.00
		uart_csr_rw	0.680s	15.580us	20	20	100.00
		uart_csr_aliasing	0.930s	27.035us	5	5	100.00
		uart_same_csr_outstanding	0.820s	32.261us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	0.880s	66.201us	5	5	100.00
		uart_tl_intg_err	1.420s	342.234us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.420s	342.234us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	28.599m	175.401ms	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1319	1320	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.10	97.65	100.00	--	98.38	100.00	99.55

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty

has 1 failures:

Test uart_intr has 1 failures.

40.uart_intr.76800474235759839490493874503807704369948465928048495623153052049000815541615
Line 281, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/40.uart_intr/latest/run.log

  UVM_ERROR @ 29198292266 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 29198292266 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 30235511090 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr
  UVM_INFO @ 32319580394 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]