UART Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: `aad711e1bc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	44.850s	10.538ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.020s	1.035ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.690s	31.151us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.240s	214.013us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.850s	38.308us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.250s	26.641us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.690s	31.151us	20	20	100.00
		uart_csr_aliasing	0.850s	38.308us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.304m	45.821ms	50	50	100.00
V2	parity	uart_smoke	44.850s	10.538ms	50	50	100.00
		uart_tx_rx	3.304m	45.821ms	50	50	100.00
V2	parity_error	uart_intr	10.849m	430.140ms	50	50	100.00
		uart_rx_parity_err	13.766m	135.017ms	50	50	100.00
V2	watermark	uart_tx_rx	3.304m	45.821ms	50	50	100.00
		uart_intr	10.849m	430.140ms	50	50	100.00
V2	fifo_full	uart_fifo_full	6.791m	165.747ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	8.990m	218.152ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	10.372m	380.171ms	299	300	99.67
V2	rx_frame_err	uart_intr	10.849m	430.140ms	50	50	100.00
V2	rx_break_err	uart_intr	10.849m	430.140ms	50	50	100.00
V2	rx_timeout	uart_intr	10.849m	430.140ms	50	50	100.00
V2	perf	uart_perf	27.742m	28.827ms	49	50	98.00
V2	sys_loopback	uart_loopback	27.570s	8.393ms	50	50	100.00
V2	line_loopback	uart_loopback	27.570s	8.393ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.845m	131.717ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.253m	47.663ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	29.220s	6.769ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.161m	7.765ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	25.949m	161.521ms	50	50	100.00
V2	stress_all	uart_stress_all	45.746m	439.759ms	48	50	96.00
V2	alert_test	uart_alert_test	0.630s	15.465us	50	50	100.00
V2	intr_test	uart_intr_test	0.660s	42.667us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.600s	294.407us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.600s	294.407us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.020s	1.035ms	5	5	100.00
		uart_csr_rw	0.690s	31.151us	20	20	100.00
		uart_csr_aliasing	0.850s	38.308us	5	5	100.00
		uart_same_csr_outstanding	0.780s	16.883us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.020s	1.035ms	5	5	100.00
		uart_csr_rw	0.690s	31.151us	20	20	100.00
		uart_csr_aliasing	0.850s	38.308us	5	5	100.00
		uart_same_csr_outstanding	0.780s	16.883us	20	20	100.00
V2		TOTAL			1086	1090	99.63
V2S	tl_intg_err	uart_sec_cm	0.880s	171.478us	5	5	100.00
		uart_tl_intg_err	1.410s	327.863us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.410s	327.863us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	33.041m	528.538ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1315	1320	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	15	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.57

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 4 failures:

Test uart_perf has 1 failures.

35.uart_perf.106067431485671229339565093262263407438125968764833955225469267377083868900200
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/35.uart_perf/latest/run.log

  UVM_ERROR @  12066099 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 490624089 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/9
  UVM_INFO @ 3354782077 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/9
  UVM_INFO @ 6122566099 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/9
  UVM_INFO @ 10509450475 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/9

Test uart_stress_all has 2 failures.

42.uart_stress_all.98227880711603700648833680007004622571794250423595341112559463111496593393490
Line 288, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/42.uart_stress_all/latest/run.log

  UVM_ERROR @ 167983654138 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 169027495822 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxTimeout
  UVM_INFO @ 189862051386 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxParityErr

43.uart_stress_all.16690855733607095917611792068450190429958014337647874771223615550060013018250
Line 284, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/43.uart_stress_all/latest/run.log

  UVM_ERROR @ 7807364924 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 7857835289 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxDone
  UVM_INFO @ 8430843208 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 2/3
  UVM_INFO @ 8431093216 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

Test uart_fifo_reset has 1 failures.

157.uart_fifo_reset.26507325183187138399683291596187984012010965376518548812014191670185235481505
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/157.uart_fifo_reset/latest/run.log

  UVM_ERROR @   1163546 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 667590927 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/5
  UVM_INFO @ 2859027090 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/5
  UVM_INFO @ 5493974727 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/5
  UVM_INFO @ 38858365270 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/5

UVM_ERROR (cip_base_vseq.sv:749) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

1.uart_stress_all_with_rand_reset.74844537026675250560603291423903203759875751999956064863375125666241130366781
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  12479379 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  12479379 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @  13034939 ps: (cip_base_vseq.sv:760) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 1/5