UART Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: `8b2da8db5e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	28.910s	5.555ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.610s	20.665us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	58.105us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.530s	1.034ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.850s	29.089us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.370s	130.350us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	58.105us	20	20	100.00
		uart_csr_aliasing	0.850s	29.089us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.644m	118.769ms	50	50	100.00
V2	parity	uart_smoke	28.910s	5.555ms	50	50	100.00
		uart_tx_rx	4.644m	118.769ms	50	50	100.00
V2	parity_error	uart_intr	12.106m	511.292ms	50	50	100.00
		uart_rx_parity_err	8.601m	323.045ms	50	50	100.00
V2	watermark	uart_tx_rx	4.644m	118.769ms	50	50	100.00
		uart_intr	12.106m	511.292ms	50	50	100.00
V2	fifo_full	uart_fifo_full	5.159m	164.753ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.879m	239.567ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.223m	134.084ms	299	300	99.67
V2	rx_frame_err	uart_intr	12.106m	511.292ms	50	50	100.00
V2	rx_break_err	uart_intr	12.106m	511.292ms	50	50	100.00
V2	rx_timeout	uart_intr	12.106m	511.292ms	50	50	100.00
V2	perf	uart_perf	29.956m	38.686ms	50	50	100.00
V2	sys_loopback	uart_loopback	32.640s	10.183ms	50	50	100.00
V2	line_loopback	uart_loopback	32.640s	10.183ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	8.854m	129.802ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.137m	83.762ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	22.760s	6.524ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.152m	7.294ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	24.736m	165.137ms	50	50	100.00
V2	stress_all	uart_stress_all	31.516m	171.789ms	50	50	100.00
V2	alert_test	uart_alert_test	0.620s	42.144us	50	50	100.00
V2	intr_test	uart_intr_test	0.630s	22.866us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.630s	304.689us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.630s	304.689us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.610s	20.665us	5	5	100.00
		uart_csr_rw	0.650s	58.105us	20	20	100.00
		uart_csr_aliasing	0.850s	29.089us	5	5	100.00
		uart_same_csr_outstanding	0.810s	17.046us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.610s	20.665us	5	5	100.00
		uart_csr_rw	0.650s	58.105us	20	20	100.00
		uart_csr_aliasing	0.850s	29.089us	5	5	100.00
		uart_same_csr_outstanding	0.810s	17.046us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	0.850s	90.747us	5	5	100.00
		uart_tl_intg_err	1.480s	328.228us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.480s	328.228us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	41.813m	96.711ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1317	1320	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.10	97.65	100.00	--	98.38	100.00	99.55

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 1 failures:

Test uart_fifo_reset has 1 failures.

13.uart_fifo_reset.14576362753267127811573623551424577775154146833681599666143426206264411512270
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/13.uart_fifo_reset/latest/run.log

  UVM_ERROR @    850709 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 6225984911 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/9
  UVM_INFO @ 6587113097 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/9
  UVM_INFO @ 9267921011 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/9
  UVM_INFO @ 11958526523 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/9

UVM_ERROR (cip_base_vseq.sv:758) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

13.uart_stress_all_with_rand_reset.868725843277172380135734687474258783059174196424500371706931517252941858957
Line 316, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 17804096601 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 17804096601 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 17804179935 ps: (cip_base_vseq.sv:770) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 1/5

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_noise_filter has 1 failures.
  - 31.uart_noise_filter.109951657462106766963528699714605373467780640771693814974961466802670602351468
    Line 266, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/31.uart_noise_filter/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```