UART Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: `974aaab627`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	35.230s	10.521ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	61.031us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.690s	19.187us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.490s	981.200us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.790s	88.101us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.430s	32.947us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.690s	19.187us	20	20	100.00
		uart_csr_aliasing	0.790s	88.101us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	5.164m	131.292ms	50	50	100.00
V2	parity	uart_smoke	35.230s	10.521ms	50	50	100.00
		uart_tx_rx	5.164m	131.292ms	50	50	100.00
V2	parity_error	uart_intr	7.026m	273.137ms	50	50	100.00
		uart_rx_parity_err	6.651m	203.313ms	50	50	100.00
V2	watermark	uart_tx_rx	5.164m	131.292ms	50	50	100.00
		uart_intr	7.026m	273.137ms	50	50	100.00
V2	fifo_full	uart_fifo_full	8.601m	288.865ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.760m	180.868ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	12.950m	327.161ms	300	300	100.00
V2	rx_frame_err	uart_intr	7.026m	273.137ms	50	50	100.00
V2	rx_break_err	uart_intr	7.026m	273.137ms	50	50	100.00
V2	rx_timeout	uart_intr	7.026m	273.137ms	50	50	100.00
V2	perf	uart_perf	26.730m	26.750ms	50	50	100.00
V2	sys_loopback	uart_loopback	19.270s	10.231ms	50	50	100.00
V2	line_loopback	uart_loopback	19.270s	10.231ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.270m	301.984ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.287m	47.460ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	27.650s	6.634ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.164m	7.764ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	31.757m	239.710ms	49	50	98.00
V2	stress_all	uart_stress_all	40.289m	698.412ms	50	50	100.00
V2	alert_test	uart_alert_test	0.640s	14.189us	50	50	100.00
V2	intr_test	uart_intr_test	0.620s	27.919us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.390s	580.715us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.390s	580.715us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	61.031us	5	5	100.00
		uart_csr_rw	0.690s	19.187us	20	20	100.00
		uart_csr_aliasing	0.790s	88.101us	5	5	100.00
		uart_same_csr_outstanding	0.840s	28.802us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	61.031us	5	5	100.00
		uart_csr_rw	0.690s	19.187us	20	20	100.00
		uart_csr_aliasing	0.790s	88.101us	5	5	100.00
		uart_same_csr_outstanding	0.840s	28.802us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	0.900s	100.571us	5	5	100.00
		uart_tl_intg_err	1.350s	118.888us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.350s	118.888us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	55.221m	195.271ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1317	1320	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.10	97.65	100.00	--	98.38	100.00	99.53

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:758) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

47.uart_stress_all_with_rand_reset.39267662138675180349304883711756287815733497903996593657322146727758129805694
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  14621731 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  14621731 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @  14941731 ps: (cip_base_vseq.sv:770) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 1/10

UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

Test uart_long_xfer_wo_dly has 1 failures.

49.uart_long_xfer_wo_dly.83686617567190980998424440821364118049499891027765869216781136014690560559629
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/49.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @ 12581897838 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_INFO @ 13819025382 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/6
  UVM_INFO @ 22989216390 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/6
  UVM_INFO @ 28845557358 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 4/6
  UVM_INFO @ 35186313966 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 5/6

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

73.uart_stress_all_with_rand_reset.3822512817878325076678041090337794188849815798905463492298948897877479715612
Line 472, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/73.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 53709503975 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 53753286321 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 44/60
  UVM_INFO @ 53821155479 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxDone
  UVM_INFO @ 53877589923 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 45/60