UART Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	25.110s	5.983ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.650s	14.967us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.630s	31.036us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.740s	253.279us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.790s	115.964us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.110s	25.485us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.630s	31.036us	20	20	100.00
		uart_csr_aliasing	0.790s	115.964us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.867m	122.667ms	50	50	100.00
V2	parity	uart_smoke	25.110s	5.983ms	50	50	100.00
		uart_tx_rx	3.867m	122.667ms	50	50	100.00
V2	parity_error	uart_intr	8.042m	257.907ms	50	50	100.00
		uart_rx_parity_err	5.233m	135.922ms	50	50	100.00
V2	watermark	uart_tx_rx	3.867m	122.667ms	50	50	100.00
		uart_intr	8.042m	257.907ms	50	50	100.00
V2	fifo_full	uart_fifo_full	5.944m	125.364ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	3.708m	145.319ms	49	50	98.00
V2	fifo_reset	uart_fifo_reset	11.280m	269.204ms	300	300	100.00
V2	rx_frame_err	uart_intr	8.042m	257.907ms	50	50	100.00
V2	rx_break_err	uart_intr	8.042m	257.907ms	50	50	100.00
V2	rx_timeout	uart_intr	8.042m	257.907ms	50	50	100.00
V2	perf	uart_perf	20.977m	21.369ms	50	50	100.00
V2	sys_loopback	uart_loopback	57.410s	7.904ms	50	50	100.00
V2	line_loopback	uart_loopback	57.410s	7.904ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.411m	144.632ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.974m	76.028ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	21.120s	7.289ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.061m	7.483ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	25.247m	179.638ms	50	50	100.00
V2	stress_all	uart_stress_all	29.984m	44.482ms	49	50	98.00
V2	alert_test	uart_alert_test	0.660s	13.702us	50	50	100.00
V2	intr_test	uart_intr_test	0.620s	10.807us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.560s	457.125us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.560s	457.125us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.650s	14.967us	5	5	100.00
		uart_csr_rw	0.630s	31.036us	20	20	100.00
		uart_csr_aliasing	0.790s	115.964us	5	5	100.00
		uart_same_csr_outstanding	0.790s	104.535us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.650s	14.967us	5	5	100.00
		uart_csr_rw	0.630s	31.036us	20	20	100.00
		uart_csr_aliasing	0.790s	115.964us	5	5	100.00
		uart_same_csr_outstanding	0.790s	104.535us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	0.880s	110.781us	5	5	100.00
		uart_tl_intg_err	1.510s	1.001ms	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.510s	1.001ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	26.989m	165.099ms	97	100	97.00
V3		TOTAL			97	100	97.00
		TOTAL			1315	1320	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.13	99.10	97.65	100.00	--	98.38	100.00	99.64

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty

has 5 failures:

Test uart_fifo_overflow has 1 failures.

16.uart_fifo_overflow.57759344525048474033004055014153817527219617052095573743048644614848375695196
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/16.uart_fifo_overflow/latest/run.log

  UVM_ERROR @  10208569 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 4018050715 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 1/7
  UVM_INFO @ 8369046364 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 2/7
  UVM_INFO @ 19147881739 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 3/7
  UVM_INFO @ 19265112391 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 4/7

Test uart_stress_all_with_rand_reset has 3 failures.

17.uart_stress_all_with_rand_reset.56853382942981886005801538506103852691184324521770594639863777800343304585005
Line 618, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 263247571072 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 263331271072 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr
  UVM_INFO @ 263489271072 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 2/3
  UVM_INFO @ 263490071072 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

46.uart_stress_all_with_rand_reset.102418673769795910850719518291778779008413165435048091492572590071240884926552
Line 571, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 341111869016 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 341185293118 ps: (cip_base_vseq.sv:762) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 5/10
  UVM_INFO @ 341185893118 ps: (cip_base_vseq.sv:770) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 5/10

... and 1 more failures.

Test uart_stress_all has 1 failures.

22.uart_stress_all.61576137357329679168189330161872160137982650936298232250608593728678118199531
Line 339, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/22.uart_stress_all/latest/run.log

  UVM_ERROR @ 373592012595 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 373639672595 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty
  UVM_INFO @ 373735172595 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxTimeout