UART Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	24.560s	6.171ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.600s	15.959us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.660s	15.179us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.630s	220.237us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.820s	49.910us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.280s	215.950us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.660s	15.179us	20	20	100.00
		uart_csr_aliasing	0.820s	49.910us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	7.700m	134.148ms	50	50	100.00
V2	parity	uart_smoke	24.560s	6.171ms	50	50	100.00
		uart_tx_rx	7.700m	134.148ms	50	50	100.00
V2	parity_error	uart_intr	6.179m	220.024ms	50	50	100.00
		uart_rx_parity_err	3.667m	143.389ms	50	50	100.00
V2	watermark	uart_tx_rx	7.700m	134.148ms	50	50	100.00
		uart_intr	6.179m	220.024ms	50	50	100.00
V2	fifo_full	uart_fifo_full	12.597m	138.399ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	4.561m	143.191ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.174m	101.064ms	299	300	99.67
V2	rx_frame_err	uart_intr	6.179m	220.024ms	50	50	100.00
V2	rx_break_err	uart_intr	6.179m	220.024ms	50	50	100.00
V2	rx_timeout	uart_intr	6.179m	220.024ms	50	50	100.00
V2	perf	uart_perf	20.693m	22.966ms	50	50	100.00
V2	sys_loopback	uart_loopback	22.560s	12.433ms	50	50	100.00
V2	line_loopback	uart_loopback	22.560s	12.433ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	7.442m	98.116ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.643m	67.354ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	27.780s	6.736ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.048m	6.853ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	18.184m	132.686ms	50	50	100.00
V2	stress_all	uart_stress_all	26.763m	207.887ms	49	50	98.00
V2	alert_test	uart_alert_test	0.610s	14.143us	50	50	100.00
V2	intr_test	uart_intr_test	0.620s	15.003us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.850s	140.268us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.850s	140.268us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.600s	15.959us	5	5	100.00
		uart_csr_rw	0.660s	15.179us	20	20	100.00
		uart_csr_aliasing	0.820s	49.910us	5	5	100.00
		uart_same_csr_outstanding	0.790s	55.773us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.600s	15.959us	5	5	100.00
		uart_csr_rw	0.660s	15.179us	20	20	100.00
		uart_csr_aliasing	0.820s	49.910us	5	5	100.00
		uart_same_csr_outstanding	0.790s	55.773us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	0.880s	55.859us	5	5	100.00
		uart_tl_intg_err	1.410s	308.524us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.410s	308.524us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	26.025m	70.065ms	97	100	97.00
V3		TOTAL			97	100	97.00
		TOTAL			1315	1320	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.10	97.65	100.00	--	98.38	100.00	99.55

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 4 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

29.uart_stress_all_with_rand_reset.94150260710964748012499161472894359716991060963160895446067208574810125883598
Line 919, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 38665456594 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 38708820187 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxWatermark
  UVM_INFO @ 38728799965 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 48/970
  UVM_INFO @ 38826163504 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 49/970

69.uart_stress_all_with_rand_reset.8929253262608331625343542747829380677007890722966643540060979110878948119201
Line 832, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 172024327055 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 172118327807 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxOverflow
  UVM_INFO @ 172542278567 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 27/439
  UVM_INFO @ 173076072311 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 28/439

Test uart_stress_all has 1 failures.

29.uart_stress_all.82893842002726450984354914544986194932480143037439724313113562060509979674684
Line 274, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/29.uart_stress_all/latest/run.log

  UVM_ERROR @ 15324588808 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 15324588808 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 15425644125 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxDone
  UVM_INFO @ 17908931921 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

Test uart_fifo_reset has 1 failures.

260.uart_fifo_reset.11948343921282620340766910039659787858494303711379312800948028905366081022928
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/260.uart_fifo_reset/latest/run.log

  UVM_ERROR @   5380233 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 1170056217 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/5
  UVM_INFO @ 2291215557 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/5
  UVM_INFO @ 33388813965 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/5
  UVM_INFO @ 66942165723 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/5

UVM_ERROR (uart_intr_vseq.sv:312) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

74.uart_stress_all_with_rand_reset.46723883456892028538206982034623362171240210372667674230911549274673732080975
Line 316, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 18703133192 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 18703133192 ps: (uart_intr_vseq.sv:314) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[uart_intr] == exp_pin (1 [0x1] vs 0 [0x0]) uart_intr name/val: RxTimeout/6, en_intr: 14d
  UVM_INFO @ 18736269887 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 12/123
  UVM_INFO @ 18981635977 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 13/123
  UVM_ERROR @ 19024045492 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])