UART Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	36.040s	11.096ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.280s	1.044ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	24.840us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.610s	259.619us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.820s	31.945us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.470s	96.224us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	24.840us	20	20	100.00
		uart_csr_aliasing	0.820s	31.945us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.016m	114.444ms	49	50	98.00
V2	parity	uart_smoke	36.040s	11.096ms	50	50	100.00
		uart_tx_rx	4.016m	114.444ms	49	50	98.00
V2	parity_error	uart_intr	18.505m	708.485ms	50	50	100.00
		uart_rx_parity_err	11.020m	228.623ms	50	50	100.00
V2	watermark	uart_tx_rx	4.016m	114.444ms	49	50	98.00
		uart_intr	18.505m	708.485ms	50	50	100.00
V2	fifo_full	uart_fifo_full	5.413m	312.098ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.548m	273.209ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.985m	327.246ms	300	300	100.00
V2	rx_frame_err	uart_intr	18.505m	708.485ms	50	50	100.00
V2	rx_break_err	uart_intr	18.505m	708.485ms	50	50	100.00
V2	rx_timeout	uart_intr	18.505m	708.485ms	50	50	100.00
V2	perf	uart_perf	23.816m	25.766ms	50	50	100.00
V2	sys_loopback	uart_loopback	26.220s	9.082ms	50	50	100.00
V2	line_loopback	uart_loopback	26.220s	9.082ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.301m	68.459ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.109m	42.048ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	32.120s	6.054ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.111m	8.255ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	25.037m	163.790ms	50	50	100.00
V2	stress_all	uart_stress_all	33.895m	416.940ms	48	50	96.00
V2	alert_test	uart_alert_test	0.640s	21.905us	50	50	100.00
V2	intr_test	uart_intr_test	0.690s	30.428us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.330s	1.486ms	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.330s	1.486ms	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.280s	1.044ms	5	5	100.00
		uart_csr_rw	0.650s	24.840us	20	20	100.00
		uart_csr_aliasing	0.820s	31.945us	5	5	100.00
		uart_same_csr_outstanding	0.830s	120.795us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.280s	1.044ms	5	5	100.00
		uart_csr_rw	0.650s	24.840us	20	20	100.00
		uart_csr_aliasing	0.820s	31.945us	5	5	100.00
		uart_same_csr_outstanding	0.830s	120.795us	20	20	100.00
V2		TOTAL			1087	1090	99.72
V2S	tl_intg_err	uart_sec_cm	0.860s	60.538us	5	5	100.00
		uart_tl_intg_err	1.620s	366.023us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.620s	366.023us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	28.722m	457.449ms	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1317	1320	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.13	99.10	97.65	100.00	--	98.38	100.00	99.66

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty

has 3 failures:

Test uart_stress_all has 2 failures.

22.uart_stress_all.66322726282038948971114183798235260022253529003986949995878291854598924140745
Line 272, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/22.uart_stress_all/latest/run.log

  UVM_ERROR @ 10773032172 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 10773032172 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 11823274112 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr
  UVM_INFO @ 22240534537 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

31.uart_stress_all.72050153831354219782302577902522615549688877771106893718669766376770845559710
Line 267, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/31.uart_stress_all/latest/run.log

  UVM_ERROR @ 133539204017 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 133539204017 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 134584312295 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr
  UVM_INFO @ 140938773122 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

Test uart_tx_rx has 1 failures.

31.uart_tx_rx.20439723231121697231165229709186018456316370101593071728384752450803252336590
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/31.uart_tx_rx/latest/run.log

  UVM_ERROR @   6747412 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 655062884 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 1/14
  UVM_INFO @ 2274697704 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 2/14
  UVM_INFO @ 5430735576 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 3/14
  UVM_INFO @ 7414643998 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_tx_rx_vseq] finished run 4/14