UART Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	38.180s	6.191ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.600s	11.760us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.730s	14.424us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.510s	170.114us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.840s	47.303us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.230s	410.258us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.730s	14.424us	20	20	100.00
		uart_csr_aliasing	0.840s	47.303us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.778m	123.181ms	50	50	100.00
V2	parity	uart_smoke	38.180s	6.191ms	50	50	100.00
		uart_tx_rx	3.778m	123.181ms	50	50	100.00
V2	parity_error	uart_intr	11.088m	404.556ms	50	50	100.00
		uart_rx_parity_err	6.140m	226.363ms	50	50	100.00
V2	watermark	uart_tx_rx	3.778m	123.181ms	50	50	100.00
		uart_intr	11.088m	404.556ms	50	50	100.00
V2	fifo_full	uart_fifo_full	9.490m	129.933ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.000m	215.907ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	11.736m	235.372ms	300	300	100.00
V2	rx_frame_err	uart_intr	11.088m	404.556ms	50	50	100.00
V2	rx_break_err	uart_intr	11.088m	404.556ms	50	50	100.00
V2	rx_timeout	uart_intr	11.088m	404.556ms	50	50	100.00
V2	perf	uart_perf	23.832m	23.866ms	50	50	100.00
V2	sys_loopback	uart_loopback	35.770s	9.675ms	50	50	100.00
V2	line_loopback	uart_loopback	35.770s	9.675ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.240m	86.348ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.046m	43.994ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	22.150s	6.121ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.084m	7.011ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	23.099m	141.039ms	50	50	100.00
V2	stress_all	uart_stress_all	30.253m	286.912ms	50	50	100.00
V2	alert_test	uart_alert_test	0.640s	22.156us	50	50	100.00
V2	intr_test	uart_intr_test	0.680s	194.591us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.840s	130.173us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.840s	130.173us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.600s	11.760us	5	5	100.00
		uart_csr_rw	0.730s	14.424us	20	20	100.00
		uart_csr_aliasing	0.840s	47.303us	5	5	100.00
		uart_same_csr_outstanding	0.840s	17.019us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.600s	11.760us	5	5	100.00
		uart_csr_rw	0.730s	14.424us	20	20	100.00
		uart_csr_aliasing	0.840s	47.303us	5	5	100.00
		uart_same_csr_outstanding	0.840s	17.019us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	0.900s	161.878us	5	5	100.00
		uart_tl_intg_err	1.390s	70.919us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.390s	70.919us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	28.704m	201.651ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1317	1320	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.10	97.65	100.00	--	98.38	100.00	99.55

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

17.uart_stress_all_with_rand_reset.100159039486949534530389821975889351686263792210986071024329591727964629733256
Line 735, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 102222650616 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 102222650616 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 102272166646 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxDone
  UVM_INFO @ 102289279515 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 26/435

98.uart_stress_all_with_rand_reset.112104131525462445448197446326571994561370327793948036185767905004495911430415
Line 1100, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 402598102245 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 402693185198 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty
  UVM_INFO @ 402884101101 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxWatermark

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_noise_filter has 1 failures.
  - 14.uart_noise_filter.14007332966010893955929117336283147128293198719740717727946917204044425445361
    Line 263, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/14.uart_noise_filter/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```