UART Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	59.960s	11.094ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.640s	58.887us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	14.151us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.410s	707.925us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.810s	93.866us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.550s	111.222us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	14.151us	20	20	100.00
		uart_csr_aliasing	0.810s	93.866us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.715m	110.452ms	50	50	100.00
V2	parity	uart_smoke	59.960s	11.094ms	50	50	100.00
		uart_tx_rx	3.715m	110.452ms	50	50	100.00
V2	parity_error	uart_intr	8.216m	298.491ms	49	50	98.00
		uart_rx_parity_err	7.094m	168.284ms	50	50	100.00
V2	watermark	uart_tx_rx	3.715m	110.452ms	50	50	100.00
		uart_intr	8.216m	298.491ms	49	50	98.00
V2	fifo_full	uart_fifo_full	4.217m	141.557ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	4.683m	63.630ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.715m	132.027ms	300	300	100.00
V2	rx_frame_err	uart_intr	8.216m	298.491ms	49	50	98.00
V2	rx_break_err	uart_intr	8.216m	298.491ms	49	50	98.00
V2	rx_timeout	uart_intr	8.216m	298.491ms	49	50	98.00
V2	perf	uart_perf	27.780m	27.674ms	50	50	100.00
V2	sys_loopback	uart_loopback	19.800s	3.355ms	50	50	100.00
V2	line_loopback	uart_loopback	19.800s	3.355ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	9.713m	84.487ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.924m	76.196ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	43.700s	12.562ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.026m	6.284ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	25.704m	163.768ms	49	50	98.00
V2	stress_all	uart_stress_all	32.854m	65.119ms	49	50	98.00
V2	alert_test	uart_alert_test	0.610s	21.133us	50	50	100.00
V2	intr_test	uart_intr_test	0.660s	12.168us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.340s	666.135us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.340s	666.135us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.640s	58.887us	5	5	100.00
		uart_csr_rw	0.650s	14.151us	20	20	100.00
		uart_csr_aliasing	0.810s	93.866us	5	5	100.00
		uart_same_csr_outstanding	0.790s	18.042us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.640s	58.887us	5	5	100.00
		uart_csr_rw	0.650s	14.151us	20	20	100.00
		uart_csr_aliasing	0.810s	93.866us	5	5	100.00
		uart_same_csr_outstanding	0.790s	18.042us	20	20	100.00
V2		TOTAL			1086	1090	99.63
V2S	tl_intg_err	uart_sec_cm	0.850s	200.044us	5	5	100.00
		uart_tl_intg_err	1.370s	1.240ms	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.370s	1.240ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	34.738m	122.691ms	97	100	97.00
V3		TOTAL			97	100	97.00
		TOTAL			1313	1320	99.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	14	77.78
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.10	97.65	100.00	--	98.38	100.00	99.53

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 4 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

17.uart_stress_all_with_rand_reset.39263457373677446922226786825664822845360751579277939961402212821920270478353
Line 472, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 24852344131 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 24890405051 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 136/918
  UVM_INFO @ 24938057731 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxOverflow
  UVM_INFO @ 24983363491 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 137/918

55.uart_stress_all_with_rand_reset.109494431867294940923471643214689144496692818921919128492535691696510304954239
Line 456, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/55.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 48304300029 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 48349260029 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr
  UVM_INFO @ 48406260029 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 44/784
  UVM_INFO @ 48460700029 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

Test uart_stress_all has 1 failures.

17.uart_stress_all.90914231161025031947216097897327082671844738535782421427868442713422396498175
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/17.uart_stress_all/latest/run.log

  UVM_ERROR @  14864155 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @  65419660 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxParityErr
  UVM_INFO @ 117864052 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxDone

Test uart_long_xfer_wo_dly has 1 failures.

45.uart_long_xfer_wo_dly.2360797343494676548135805852223472429951706976689300816061098362135199295632
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/45.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @    870592 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 34423026513 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/10
  UVM_INFO @ 40913477041 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/10
  UVM_INFO @ 71056679692 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/10
  UVM_INFO @ 72759053828 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 4/10

UVM_ERROR (uart_intr_vseq.sv:312) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 1 failures:

Test uart_intr has 1 failures.

5.uart_intr.48473751321849135918471708508264086973760399265696125907096366662774055566325
Line 277, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/5.uart_intr/latest/run.log

  UVM_ERROR @ 28482684228 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 28689284228 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 28853684228 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 29035884228 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 29351884228 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_noise_filter has 1 failures.
  - 11.uart_noise_filter.67694523007709832401342106871430796398802323364874555101004343128352275748705
    Line 267, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/11.uart_noise_filter/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (uart_intr_vseq.sv:325) [uart_intr_vseq] Check failed act_intr_state & exp_mask == exp (* [*] vs * [*]) has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

23.uart_stress_all_with_rand_reset.11660631661025335280700366176437786232681378183482139163540604125759456669606
Line 464, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/23.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 81583460419 ps: (uart_intr_vseq.sv:325) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state & exp_mask == exp (16 [0x10] vs 0 [0x0])
  UVM_ERROR @ 81583460419 ps: (uart_intr_vseq.sv:327) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed cfg.intr_vif.pins[NumUartIntr-1:0] & exp_mask == exp_pin (16 [0x10] vs 0 [0x0]) uart_intr val: 0, en_intr: b6
  UVM_INFO @ 82216316929 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty
  UVM_INFO @ 82349888224 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]