UART Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: `e4c5daa580`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	40.450s	11.635ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	16.388us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	13.916us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.560s	786.682us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.770s	50.772us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.300s	27.756us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	13.916us	20	20	100.00
		uart_csr_aliasing	0.770s	50.772us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.849m	152.592ms	50	50	100.00
V2	parity	uart_smoke	40.450s	11.635ms	50	50	100.00
		uart_tx_rx	4.849m	152.592ms	50	50	100.00
V2	parity_error	uart_intr	8.796m	354.611ms	50	50	100.00
		uart_rx_parity_err	6.860m	289.038ms	50	50	100.00
V2	watermark	uart_tx_rx	4.849m	152.592ms	50	50	100.00
		uart_intr	8.796m	354.611ms	50	50	100.00
V2	fifo_full	uart_fifo_full	7.170m	160.255ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	4.242m	184.965ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	11.738m	93.304ms	300	300	100.00
V2	rx_frame_err	uart_intr	8.796m	354.611ms	50	50	100.00
V2	rx_break_err	uart_intr	8.796m	354.611ms	50	50	100.00
V2	rx_timeout	uart_intr	8.796m	354.611ms	50	50	100.00
V2	perf	uart_perf	23.647m	26.815ms	50	50	100.00
V2	sys_loopback	uart_loopback	24.990s	7.679ms	50	50	100.00
V2	line_loopback	uart_loopback	24.990s	7.679ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.091m	120.483ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.080m	39.374ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	37.780s	6.374ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.176m	7.364ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	19.257m	182.413ms	50	50	100.00
V2	stress_all	uart_stress_all	41.899m	508.996ms	48	50	96.00
V2	alert_test	uart_alert_test	0.610s	50.805us	50	50	100.00
V2	intr_test	uart_intr_test	0.640s	16.746us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.290s	143.045us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.290s	143.045us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	16.388us	5	5	100.00
		uart_csr_rw	0.650s	13.916us	20	20	100.00
		uart_csr_aliasing	0.770s	50.772us	5	5	100.00
		uart_same_csr_outstanding	0.830s	25.719us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	16.388us	5	5	100.00
		uart_csr_rw	0.650s	13.916us	20	20	100.00
		uart_csr_aliasing	0.770s	50.772us	5	5	100.00
		uart_same_csr_outstanding	0.830s	25.719us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	0.870s	210.429us	5	5	100.00
		uart_tl_intg_err	1.350s	90.736us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.350s	90.736us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	40.941m	185.703ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1317	1320	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.10	97.65	100.00	--	98.38	100.00	99.53

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:755) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

18.uart_stress_all_with_rand_reset.29831991852236690985152314824484385605372262730911640519442892041325479485202
Line 571, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 28547703888 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 28547703888 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 3/5
  UVM_INFO @ 28547703888 ps: (csr_utils_pkg.sv:355) [csr_utils] Early-exit from csr_rd_sub because we are in reset
  UVM_INFO @ 28547704610 ps: (csr_utils_pkg.sv:355) [csr_utils] Early-exit from csr_rd_sub because we are in reset

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 1 failures:

Test uart_stress_all has 1 failures.

22.uart_stress_all.68503113034165109044692188962135219192359524014012333455962050004185109440577
Line 273, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/22.uart_stress_all/latest/run.log

  UVM_ERROR @ 122681581761 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 122995007825 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/10
  UVM_INFO @ 123678696233 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/10
  UVM_INFO @ 123681002337 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/10
  UVM_INFO @ 130874341765 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/10

UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

Test uart_stress_all has 1 failures.

37.uart_stress_all.95548151305190066506984777887553619928052484154457523085524891390024264081889
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/37.uart_stress_all/latest/run.log

  UVM_ERROR @ 352406372 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 422642228 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 561643340 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_INFO @ 9716657756 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/5
  UVM_INFO @ 11610261140 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/5