UART Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: `5fd4ecc0fc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	31.330s	5.377ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	11.695us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.640s	18.594us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.360s	2.091ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.770s	257.934us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.500s	32.709us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	18.594us	20	20	100.00
		uart_csr_aliasing	0.770s	257.934us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	6.718m	132.852ms	50	50	100.00
V2	parity	uart_smoke	31.330s	5.377ms	50	50	100.00
		uart_tx_rx	6.718m	132.852ms	50	50	100.00
V2	parity_error	uart_intr	9.821m	314.671ms	50	50	100.00
		uart_rx_parity_err	3.364m	97.448ms	50	50	100.00
V2	watermark	uart_tx_rx	6.718m	132.852ms	50	50	100.00
		uart_intr	9.821m	314.671ms	50	50	100.00
V2	fifo_full	uart_fifo_full	11.412m	228.204ms	49	50	98.00
V2	fifo_overflow	uart_fifo_overflow	5.320m	216.308ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	11.210m	142.664ms	300	300	100.00
V2	rx_frame_err	uart_intr	9.821m	314.671ms	50	50	100.00
V2	rx_break_err	uart_intr	9.821m	314.671ms	50	50	100.00
V2	rx_timeout	uart_intr	9.821m	314.671ms	50	50	100.00
V2	perf	uart_perf	25.193m	26.115ms	50	50	100.00
V2	sys_loopback	uart_loopback	46.220s	12.317ms	50	50	100.00
V2	line_loopback	uart_loopback	46.220s	12.317ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.737m	102.681ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.980m	80.092ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	24.040s	6.655ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.153m	7.811ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	19.569m	155.293ms	50	50	100.00
V2	stress_all	uart_stress_all	27.053m	282.069ms	49	50	98.00
V2	alert_test	uart_alert_test	0.620s	48.921us	50	50	100.00
V2	intr_test	uart_intr_test	0.670s	15.550us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.560s	262.034us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.560s	262.034us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	11.695us	5	5	100.00
		uart_csr_rw	0.640s	18.594us	20	20	100.00
		uart_csr_aliasing	0.770s	257.934us	5	5	100.00
		uart_same_csr_outstanding	0.760s	31.817us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	11.695us	5	5	100.00
		uart_csr_rw	0.640s	18.594us	20	20	100.00
		uart_csr_aliasing	0.770s	257.934us	5	5	100.00
		uart_same_csr_outstanding	0.760s	31.817us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	0.850s	259.657us	5	5	100.00
		uart_tl_intg_err	1.380s	228.046us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.380s	228.046us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	25.197m	97.430ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1317	1320	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.10	97.65	100.00	--	98.38	100.00	99.53

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 2 failures:

Test uart_fifo_full has 1 failures.

15.uart_fifo_full.570219041542103483076262357756739548645432531243211803994180885996039704554
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/15.uart_fifo_full/latest/run.log

  UVM_ERROR @   8436484 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @   8436484 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 8148036484 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 1/5
  UVM_INFO @ 13501476484 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 2/5
  UVM_INFO @ 65314956484 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 3/5

Test uart_stress_all has 1 failures.

25.uart_stress_all.48917450266450024277291184086794557568168928953182180544651435240892614450860
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/25.uart_stress_all/latest/run.log

  UVM_ERROR @   4795274 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 728967734 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/8
  UVM_INFO @ 1292013905 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/8
  UVM_INFO @ 1293097247 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/8
  UVM_INFO @ 10051875650 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/8

UVM_ERROR (uart_intr_vseq.sv:312) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

20.uart_stress_all_with_rand_reset.8848301053291243841964823338261826724816914839665082223092610362660524594321
Line 627, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 652324384354 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 652556984354 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 652705184354 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/468
  UVM_ERROR @ 652790184354 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 653238378880 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]