UART Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: `bbf435ceff`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	38.290s	11.097ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.790s	1.113ms	4	5	80.00
V1	csr_rw	uart_csr_rw	0.670s	50.811us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.270s	176.472us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.840s	30.627us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.060s	19.811us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.670s	50.811us	20	20	100.00
		uart_csr_aliasing	0.840s	30.627us	5	5	100.00
V1		TOTAL			104	105	99.05
V2	base_random_seq	uart_tx_rx	3.769m	77.126ms	50	50	100.00
V2	parity	uart_smoke	38.290s	11.097ms	50	50	100.00
		uart_tx_rx	3.769m	77.126ms	50	50	100.00
V2	parity_error	uart_intr	5.957m	216.910ms	49	50	98.00
		uart_rx_parity_err	7.472m	277.488ms	50	50	100.00
V2	watermark	uart_tx_rx	3.769m	77.126ms	50	50	100.00
		uart_intr	5.957m	216.910ms	49	50	98.00
V2	fifo_full	uart_fifo_full	9.333m	132.735ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.312m	223.219ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	16.821m	305.677ms	299	300	99.67
V2	rx_frame_err	uart_intr	5.957m	216.910ms	49	50	98.00
V2	rx_break_err	uart_intr	5.957m	216.910ms	49	50	98.00
V2	rx_timeout	uart_intr	5.957m	216.910ms	49	50	98.00
V2	perf	uart_perf	19.643m	30.896ms	50	50	100.00
V2	sys_loopback	uart_loopback	21.280s	12.412ms	50	50	100.00
V2	line_loopback	uart_loopback	21.280s	12.412ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.243m	94.806ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.306m	53.648ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	47.030s	12.566ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.177m	7.236ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	24.120m	137.442ms	50	50	100.00
V2	stress_all	uart_stress_all	37.429m	253.363ms	49	50	98.00
V2	alert_test	uart_alert_test	0.650s	49.252us	50	50	100.00
V2	intr_test	uart_intr_test	0.640s	42.624us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.450s	1.529ms	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.450s	1.529ms	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.790s	1.113ms	4	5	80.00
		uart_csr_rw	0.670s	50.811us	20	20	100.00
		uart_csr_aliasing	0.840s	30.627us	5	5	100.00
		uart_same_csr_outstanding	0.790s	35.172us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.790s	1.113ms	4	5	80.00
		uart_csr_rw	0.670s	50.811us	20	20	100.00
		uart_csr_aliasing	0.840s	30.627us	5	5	100.00
		uart_same_csr_outstanding	0.790s	35.172us	20	20	100.00
V2		TOTAL			1087	1090	99.72
V2S	tl_intg_err	uart_sec_cm	0.940s	107.055us	5	5	100.00
		uart_tl_intg_err	1.400s	1.257ms	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.400s	1.257ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	30.063m	252.975ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1315	1320	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	18	18	15	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.10	97.65	100.00	--	98.38	100.00	99.53

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 3 failures:

Test uart_intr has 1 failures.

5.uart_intr.89146246836094441741330137330595614908257556899432200527734479157394324013226
Line 292, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/5.uart_intr/latest/run.log

  UVM_ERROR @ 21445549025 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 21540730748 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark
  UVM_INFO @ 21731730557 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxOverflow

Test uart_stress_all_with_rand_reset has 1 failures.

66.uart_stress_all_with_rand_reset.87626028715291450702262123486970582995098482070931850394922393038616390941308
Line 259, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/66.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 444902665 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 506720785 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/202
  UVM_INFO @ 536094493 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 8/202
  UVM_INFO @ 594619687 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 9/202
  UVM_INFO @ 652710538 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 10/202

Test uart_fifo_reset has 1 failures.

249.uart_fifo_reset.4463923080936015669031749398132823189597616250075102340394437653444122345317
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/249.uart_fifo_reset/latest/run.log

  UVM_ERROR @   1850931 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 729702779 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/6
  UVM_INFO @ 3079569123 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/6
  UVM_INFO @ 5118781629 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/6
  UVM_INFO @ 5356008962 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/6

UVM_ERROR (uart_monitor.sv:179) monitor [monitor] Expect uart_tx stable from * to * of the period, but it's changed has 1 failures:

Test uart_csr_hw_reset has 1 failures.

1.uart_csr_hw_reset.75795992273290564686137253123585799023627927569909080511112295987026305835395
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_csr_hw_reset/latest/run.log

  UVM_ERROR @  53199077 ps: (uart_monitor.sv:179) uvm_test_top.env.m_uart_agent.monitor [uvm_test_top.env.m_uart_agent.monitor] Expect uart_tx stable from 25 to 75 of the period, but it's changed
  UVM_INFO @ 1043361782 ps: (dv_base_vseq.sv:194) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running csr hw_reset vseq iteration 2/2.
  UVM_INFO @ 1113194856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

Test uart_stress_all has 1 failures.

10.uart_stress_all.84611500136268275762565582224923044275879430027432149027531660767001753972538
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/10.uart_stress_all/latest/run.log

  UVM_ERROR @ 139939247 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 285881591 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 364705751 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 375882311 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 454706471 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1