UART Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: `3707c48f56`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	29.420s	5.385ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.270s	1.038ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	17.083us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.420s	341.183us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.780s	16.454us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.390s	80.946us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	17.083us	20	20	100.00
		uart_csr_aliasing	0.780s	16.454us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.299m	97.914ms	50	50	100.00
V2	parity	uart_smoke	29.420s	5.385ms	50	50	100.00
		uart_tx_rx	3.299m	97.914ms	50	50	100.00
V2	parity_error	uart_intr	7.480m	282.620ms	49	50	98.00
		uart_rx_parity_err	12.017m	186.161ms	50	50	100.00
V2	watermark	uart_tx_rx	3.299m	97.914ms	50	50	100.00
		uart_intr	7.480m	282.620ms	49	50	98.00
V2	fifo_full	uart_fifo_full	10.369m	145.215ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.955m	166.287ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	6.602m	140.703ms	299	300	99.67
V2	rx_frame_err	uart_intr	7.480m	282.620ms	49	50	98.00
V2	rx_break_err	uart_intr	7.480m	282.620ms	49	50	98.00
V2	rx_timeout	uart_intr	7.480m	282.620ms	49	50	98.00
V2	perf	uart_perf	16.579m	16.458ms	50	50	100.00
V2	sys_loopback	uart_loopback	27.670s	9.238ms	50	50	100.00
V2	line_loopback	uart_loopback	27.670s	9.238ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.555m	116.731ms	48	50	96.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.739m	71.984ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	47.300s	6.629ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	55.850s	6.748ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	18.437m	142.052ms	50	50	100.00
V2	stress_all	uart_stress_all	19.505m	311.883ms	50	50	100.00
V2	alert_test	uart_alert_test	0.630s	10.822us	50	50	100.00
V2	intr_test	uart_intr_test	0.620s	15.918us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.530s	138.459us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.530s	138.459us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.270s	1.038ms	5	5	100.00
		uart_csr_rw	0.650s	17.083us	20	20	100.00
		uart_csr_aliasing	0.780s	16.454us	5	5	100.00
		uart_same_csr_outstanding	0.880s	32.982us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.270s	1.038ms	5	5	100.00
		uart_csr_rw	0.650s	17.083us	20	20	100.00
		uart_csr_aliasing	0.780s	16.454us	5	5	100.00
		uart_same_csr_outstanding	0.880s	32.982us	20	20	100.00
V2		TOTAL			1086	1090	99.63
V2S	tl_intg_err	uart_sec_cm	0.900s	126.811us	5	5	100.00
		uart_tl_intg_err	1.370s	295.652us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.370s	295.652us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	43.383m	120.410ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1314	1320	99.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	15	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.10	99.10	97.65	100.00	--	98.38	100.00	99.50

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 4 failures:

Test uart_noise_filter has 1 failures.

10.uart_noise_filter.67204096843840286795863705111888353364434170246442334461478733919002519540497
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/10.uart_noise_filter/latest/run.log

  UVM_ERROR @   7353404 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 8591838746 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 1/7
  UVM_INFO @ 10373769668 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 2/7
  UVM_INFO @ 10739147591 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 3/7
  UVM_INFO @ 28102036493 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 4/7

Test uart_intr has 1 failures.

28.uart_intr.36782155792945299998792432316798680680534628542485597311741564604626749578241
Line 250, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/28.uart_intr/latest/run.log

  UVM_ERROR @   3455690 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @  96655690 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr
  UVM_INFO @ 270975690 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxParityErr

Test uart_stress_all_with_rand_reset has 1 failures.

97.uart_stress_all_with_rand_reset.95172730063158653796391371662654135633701254382447775460998303556909262662213
Line 731, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/97.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 38632593979 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 38632593979 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 38677076855 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty
  UVM_INFO @ 38679887297 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 13/341

Test uart_fifo_reset has 1 failures.

230.uart_fifo_reset.77325502172980125569851175413152974618228346432316622718911709951764029350586
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/230.uart_fifo_reset/latest/run.log

  UVM_ERROR @  10987181 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 4343387181 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/9
  UVM_INFO @ 5716887181 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/9
  UVM_INFO @ 8707787181 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/9
  UVM_INFO @ 15217087181 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/9

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_noise_filter has 1 failures.
  - 28.uart_noise_filter.13232382355117010669746957752901638131194330353742013588619896944957597179658
    Line 263, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/28.uart_noise_filter/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:755) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

38.uart_stress_all_with_rand_reset.79310866831441993886514067095671248639978956900260601469714696878446968459740
Line 323, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 149937925827 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 149937925827 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 149938725827 ps: (cip_base_vseq.sv:767) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 1/5