UART Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	31.290s	11.579ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.090s	1.053ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	23.066us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.450s	626.367us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.810s	27.671us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.140s	95.503us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	23.066us	20	20	100.00
		uart_csr_aliasing	0.810s	27.671us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.984m	124.205ms	50	50	100.00
V2	parity	uart_smoke	31.290s	11.579ms	50	50	100.00
		uart_tx_rx	3.984m	124.205ms	50	50	100.00
V2	parity_error	uart_intr	13.998m	458.386ms	50	50	100.00
		uart_rx_parity_err	5.957m	194.617ms	50	50	100.00
V2	watermark	uart_tx_rx	3.984m	124.205ms	50	50	100.00
		uart_intr	13.998m	458.386ms	50	50	100.00
V2	fifo_full	uart_fifo_full	6.996m	163.504ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	8.509m	189.195ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.706m	218.785ms	300	300	100.00
V2	rx_frame_err	uart_intr	13.998m	458.386ms	50	50	100.00
V2	rx_break_err	uart_intr	13.998m	458.386ms	50	50	100.00
V2	rx_timeout	uart_intr	13.998m	458.386ms	50	50	100.00
V2	perf	uart_perf	23.989m	25.858ms	50	50	100.00
V2	sys_loopback	uart_loopback	21.670s	9.834ms	50	50	100.00
V2	line_loopback	uart_loopback	21.670s	9.834ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	7.668m	119.342ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.323m	91.133ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	1.038m	12.616ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.110m	6.950ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	24.402m	131.790ms	50	50	100.00
V2	stress_all	uart_stress_all	29.158m	586.284ms	50	50	100.00
V2	alert_test	uart_alert_test	0.620s	15.454us	50	50	100.00
V2	intr_test	uart_intr_test	0.640s	14.534us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.350s	701.081us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.350s	701.081us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.090s	1.053ms	5	5	100.00
		uart_csr_rw	0.650s	23.066us	20	20	100.00
		uart_csr_aliasing	0.810s	27.671us	5	5	100.00
		uart_same_csr_outstanding	0.780s	30.971us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.090s	1.053ms	5	5	100.00
		uart_csr_rw	0.650s	23.066us	20	20	100.00
		uart_csr_aliasing	0.810s	27.671us	5	5	100.00
		uart_same_csr_outstanding	0.780s	30.971us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	0.920s	523.962us	5	5	100.00
		uart_tl_intg_err	1.640s	1.321ms	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.640s	1.321ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	39.298m	97.110ms	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1319	1320	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.10	97.65	100.00	--	98.38	100.00	99.53

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 8.uart_noise_filter.75929377732935851231911156263770993400013231937187748719813695871738752966810
      Line 265, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/8.uart_noise_filter/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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