UART Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	33.420s	5.365ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.340s	1.039ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	19.807us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.400s	922.888us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.770s	93.350us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.330s	117.125us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	19.807us	20	20	100.00
		uart_csr_aliasing	0.770s	93.350us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	7.681m	160.224ms	49	50	98.00
V2	parity	uart_smoke	33.420s	5.365ms	50	50	100.00
		uart_tx_rx	7.681m	160.224ms	49	50	98.00
V2	parity_error	uart_intr	8.581m	312.035ms	49	50	98.00
		uart_rx_parity_err	7.474m	103.784ms	50	50	100.00
V2	watermark	uart_tx_rx	7.681m	160.224ms	49	50	98.00
		uart_intr	8.581m	312.035ms	49	50	98.00
V2	fifo_full	uart_fifo_full	7.464m	181.442ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	4.381m	125.545ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.478m	253.637ms	300	300	100.00
V2	rx_frame_err	uart_intr	8.581m	312.035ms	49	50	98.00
V2	rx_break_err	uart_intr	8.581m	312.035ms	49	50	98.00
V2	rx_timeout	uart_intr	8.581m	312.035ms	49	50	98.00
V2	perf	uart_perf	19.182m	22.081ms	50	50	100.00
V2	sys_loopback	uart_loopback	26.540s	7.040ms	50	50	100.00
V2	line_loopback	uart_loopback	26.540s	7.040ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.081m	246.921ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.466m	54.680ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	1.239m	6.765ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.140m	7.249ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	17.723m	133.492ms	50	50	100.00
V2	stress_all	uart_stress_all	22.831m	124.019ms	49	50	98.00
V2	alert_test	uart_alert_test	0.570s	30.660us	50	50	100.00
V2	intr_test	uart_intr_test	0.650s	45.547us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.360s	143.912us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.360s	143.912us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.340s	1.039ms	5	5	100.00
		uart_csr_rw	0.650s	19.807us	20	20	100.00
		uart_csr_aliasing	0.770s	93.350us	5	5	100.00
		uart_same_csr_outstanding	0.780s	50.914us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.340s	1.039ms	5	5	100.00
		uart_csr_rw	0.650s	19.807us	20	20	100.00
		uart_csr_aliasing	0.770s	93.350us	5	5	100.00
		uart_same_csr_outstanding	0.780s	50.914us	20	20	100.00
V2		TOTAL			1087	1090	99.72
V2S	tl_intg_err	uart_sec_cm	0.840s	123.785us	5	5	100.00
		uart_tl_intg_err	1.350s	196.707us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.350s	196.707us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	36.980m	275.713ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1315	1320	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	15	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.59

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 3 failures:

Test uart_intr has 1 failures.

27.uart_intr.10026207139111952512871052839389423377944439642841506471945412777975992378935
Line 275, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/27.uart_intr/latest/run.log

  UVM_ERROR @ 38210505724 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 38290297384 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty
  UVM_INFO @ 38446612751 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxOverflow

Test uart_stress_all has 1 failures.

37.uart_stress_all.101795429819360570702706122751776431674498991429598648296637331798729872591940
Line 265, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/37.uart_stress_all/latest/run.log

  UVM_ERROR @ 82670967851 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 82670967851 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 82757797851 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxDone
  UVM_INFO @ 83105287851 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

Test uart_stress_all_with_rand_reset has 1 failures.

40.uart_stress_all_with_rand_reset.25717461488534964920784534195249228677300992773210732000988336347432754950998
Line 1247, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 336875463431 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 337108076403 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/400
  UVM_INFO @ 337731081387 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/400
  UVM_INFO @ 338227640915 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/400
  UVM_INFO @ 338324086131 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/400

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_tx_rx has 1 failures.
  - 36.uart_tx_rx.68902179075559858093333344748700173711934638514077625970225898234380160321361
    Line 266, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_tx_rx/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:755) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

36.uart_stress_all_with_rand_reset.57331202578321982274525724743072266822192926587669193974159628505432170050987
Line 258, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  17665829 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  17665829 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @  17665829 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/10
  UVM_INFO @  17706645 ps: (cip_base_vseq.sv:767) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]