UART Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	25.870s	6.043ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	47.309us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.670s	40.147us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.590s	639.073us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.800s	16.234us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.370s	28.569us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.670s	40.147us	20	20	100.00
		uart_csr_aliasing	0.800s	16.234us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.611m	116.811ms	50	50	100.00
V2	parity	uart_smoke	25.870s	6.043ms	50	50	100.00
		uart_tx_rx	3.611m	116.811ms	50	50	100.00
V2	parity_error	uart_intr	8.228m	547.223ms	48	50	96.00
		uart_rx_parity_err	6.804m	121.771ms	50	50	100.00
V2	watermark	uart_tx_rx	3.611m	116.811ms	50	50	100.00
		uart_intr	8.228m	547.223ms	48	50	96.00
V2	fifo_full	uart_fifo_full	6.279m	155.697ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.229m	111.132ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	12.565m	210.276ms	300	300	100.00
V2	rx_frame_err	uart_intr	8.228m	547.223ms	48	50	96.00
V2	rx_break_err	uart_intr	8.228m	547.223ms	48	50	96.00
V2	rx_timeout	uart_intr	8.228m	547.223ms	48	50	96.00
V2	perf	uart_perf	25.125m	25.790ms	50	50	100.00
V2	sys_loopback	uart_loopback	27.390s	13.732ms	50	50	100.00
V2	line_loopback	uart_loopback	27.390s	13.732ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.129m	115.207ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.829m	77.912ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	55.060s	12.563ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.033m	7.311ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	37.463m	205.495ms	50	50	100.00
V2	stress_all	uart_stress_all	32.378m	256.538ms	50	50	100.00
V2	alert_test	uart_alert_test	0.610s	22.291us	50	50	100.00
V2	intr_test	uart_intr_test	0.760s	16.074us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.560s	118.059us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.560s	118.059us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	47.309us	5	5	100.00
		uart_csr_rw	0.670s	40.147us	20	20	100.00
		uart_csr_aliasing	0.800s	16.234us	5	5	100.00
		uart_same_csr_outstanding	0.770s	19.895us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	47.309us	5	5	100.00
		uart_csr_rw	0.670s	40.147us	20	20	100.00
		uart_csr_aliasing	0.800s	16.234us	5	5	100.00
		uart_same_csr_outstanding	0.770s	19.895us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	1.300s	1.783ms	5	5	100.00
		uart_tl_intg_err	1.420s	213.025us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.420s	213.025us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	39.025m	82.439ms	96	100	96.00
V3		TOTAL			96	100	96.00
		TOTAL			1314	1320	99.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.10	99.10	97.65	100.00	--	98.38	100.00	99.48

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 4 failures:

Test uart_intr has 2 failures.

8.uart_intr.109180730777027546098544748947605605986175907700927797194741211228593229811375
Line 302, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/8.uart_intr/latest/run.log

  UVM_ERROR @ 27273414493 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 27320956540 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty
  UVM_INFO @ 27416457304 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 3/3
  UVM_INFO @ 27448749189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

23.uart_intr.73411375156812754578590662821557934485491707197789254964587832099648967655888
Line 273, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/23.uart_intr/latest/run.log

  UVM_ERROR @ 11779683931 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 11864508139 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr
  UVM_INFO @ 13412049931 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxWatermark

Test uart_stress_all_with_rand_reset has 2 failures.

32.uart_stress_all_with_rand_reset.91032048378722916047652128694206693238717994456091995724591558171620241735850
Line 513, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 19730320380 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 19731070380 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 113/855
  UVM_INFO @ 19835180380 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 114/855
  UVM_INFO @ 19909710380 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 115/855
  UVM_INFO @ 19965370380 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 116/855

71.uart_stress_all_with_rand_reset.89106466458174636725894426187355502572878854528284773657371109974671967440910
Line 571, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/71.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 46660675710 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 46660675710 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 46745091026 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 59/839
  UVM_INFO @ 46937858775 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 60/839
  UVM_INFO @ 47021294940 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 61/839

UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

63.uart_stress_all_with_rand_reset.31188879970122845257493784832487356587800591881750955141482998060154457790581
Line 489, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/63.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 77715195110 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 77726371670 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 78064197902 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_INFO @ 78156610406 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 27/496
  UVM_INFO @ 78635202470 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 28/496

UVM_ERROR (cip_base_vseq.sv:755) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

73.uart_stress_all_with_rand_reset.43261011123457535248682778291970415394284539435733583167686065955222215684796
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/73.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @   3456083 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @   3456083 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @   3539419 ps: (cip_base_vseq.sv:767) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 1/10