UART Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: `c082b8981f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	23.790s	6.243ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	19.022us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.680s	19.571us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.220s	891.274us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.690s	66.442us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.480s	30.529us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.680s	19.571us	20	20	100.00
		uart_csr_aliasing	0.690s	66.442us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.604m	112.248ms	50	50	100.00
V2	parity	uart_smoke	23.790s	6.243ms	50	50	100.00
		uart_tx_rx	3.604m	112.248ms	50	50	100.00
V2	parity_error	uart_intr	3.423m	107.817ms	50	50	100.00
		uart_rx_parity_err	4.062m	184.969ms	50	50	100.00
V2	watermark	uart_tx_rx	3.604m	112.248ms	50	50	100.00
		uart_intr	3.423m	107.817ms	50	50	100.00
V2	fifo_full	uart_fifo_full	7.239m	123.380ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	10.434m	92.086ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	6.741m	290.478ms	300	300	100.00
V2	rx_frame_err	uart_intr	3.423m	107.817ms	50	50	100.00
V2	rx_break_err	uart_intr	3.423m	107.817ms	50	50	100.00
V2	rx_timeout	uart_intr	3.423m	107.817ms	50	50	100.00
V2	perf	uart_perf	32.532m	33.522ms	50	50	100.00
V2	sys_loopback	uart_loopback	24.250s	11.372ms	50	50	100.00
V2	line_loopback	uart_loopback	24.250s	11.372ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.394m	140.358ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	51.730s	33.679ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	22.040s	6.641ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.072m	7.572ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	27.308m	182.205ms	50	50	100.00
V2	stress_all	uart_stress_all	38.124m	244.920ms	50	50	100.00
V2	alert_test	uart_alert_test	0.610s	28.217us	50	50	100.00
V2	intr_test	uart_intr_test	0.640s	23.958us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.380s	126.180us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.380s	126.180us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	19.022us	5	5	100.00
		uart_csr_rw	0.680s	19.571us	20	20	100.00
		uart_csr_aliasing	0.690s	66.442us	5	5	100.00
		uart_same_csr_outstanding	0.810s	34.718us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	19.022us	5	5	100.00
		uart_csr_rw	0.680s	19.571us	20	20	100.00
		uart_csr_aliasing	0.690s	66.442us	5	5	100.00
		uart_same_csr_outstanding	0.810s	34.718us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	0.930s	64.161us	5	5	100.00
		uart_tl_intg_err	1.450s	206.595us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.450s	206.595us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.018m	7.773ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1319	1320	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	18	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.10	97.65	100.00	--	98.38	100.00	99.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:767) [uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.

has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

41.uart_stress_all_with_rand_reset.5294998358036976234010737834274517008701492060354159279230378811341374463713
Line 292, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 664514094 ps: (cip_base_vseq.sv:767) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 664514094 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 5/10
  UVM_INFO @ 664554094 ps: (cip_base_vseq.sv:779) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 5/10