UART Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: `098010d125`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	40.040s	10.531ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.650s	21.386us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.630s	17.788us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.250s	58.814us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.800s	205.245us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.210s	25.578us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.630s	17.788us	20	20	100.00
		uart_csr_aliasing	0.800s	205.245us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	2.905m	78.035ms	50	50	100.00
V2	parity	uart_smoke	40.040s	10.531ms	50	50	100.00
		uart_tx_rx	2.905m	78.035ms	50	50	100.00
V2	parity_error	uart_intr	3.389m	194.817ms	50	50	100.00
		uart_rx_parity_err	5.266m	318.429ms	50	50	100.00
V2	watermark	uart_tx_rx	2.905m	78.035ms	50	50	100.00
		uart_intr	3.389m	194.817ms	50	50	100.00
V2	fifo_full	uart_fifo_full	7.399m	275.995ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	10.761m	167.452ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.599m	207.519ms	300	300	100.00
V2	rx_frame_err	uart_intr	3.389m	194.817ms	50	50	100.00
V2	rx_break_err	uart_intr	3.389m	194.817ms	50	50	100.00
V2	rx_timeout	uart_intr	3.389m	194.817ms	50	50	100.00
V2	perf	uart_perf	24.771m	24.339ms	50	50	100.00
V2	sys_loopback	uart_loopback	37.660s	8.336ms	50	50	100.00
V2	line_loopback	uart_loopback	37.660s	8.336ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.028m	298.890ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.009m	40.900ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	42.150s	7.091ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.090m	6.651ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	23.067m	164.318ms	50	50	100.00
V2	stress_all	uart_stress_all	21.861m	328.350ms	50	50	100.00
V2	alert_test	uart_alert_test	0.610s	12.882us	50	50	100.00
V2	intr_test	uart_intr_test	0.630s	243.839us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.770s	138.741us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.770s	138.741us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.650s	21.386us	5	5	100.00
		uart_csr_rw	0.630s	17.788us	20	20	100.00
		uart_csr_aliasing	0.800s	205.245us	5	5	100.00
		uart_same_csr_outstanding	0.800s	26.071us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.650s	21.386us	5	5	100.00
		uart_csr_rw	0.630s	17.788us	20	20	100.00
		uart_csr_aliasing	0.800s	205.245us	5	5	100.00
		uart_same_csr_outstanding	0.800s	26.071us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	0.920s	58.800us	5	5	100.00
		uart_tl_intg_err	1.330s	135.795us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.330s	135.795us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.676m	6.202ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1319	1320	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	18	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.59

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:771) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.

has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

45.uart_stress_all_with_rand_reset.104249909660462515793545180030567702277018969668121949785310657405227128591087
Line 383, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/45.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 28332239882 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 28332239882 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 10/10
  UVM_INFO @ 28333058063 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 10/10