UART Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: `584c3d46af`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	32.220s	5.309ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.600s	50.279us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	199.906us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.480s	266.598us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.760s	17.857us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.240s	91.715us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	199.906us	20	20	100.00
		uart_csr_aliasing	0.760s	17.857us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	6.070m	198.329ms	50	50	100.00
V2	parity	uart_smoke	32.220s	5.309ms	50	50	100.00
		uart_tx_rx	6.070m	198.329ms	50	50	100.00
V2	parity_error	uart_intr	7.833m	238.491ms	50	50	100.00
		uart_rx_parity_err	9.229m	168.560ms	50	50	100.00
V2	watermark	uart_tx_rx	6.070m	198.329ms	50	50	100.00
		uart_intr	7.833m	238.491ms	50	50	100.00
V2	fifo_full	uart_fifo_full	6.823m	245.815ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.358m	314.126ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.339m	185.532ms	300	300	100.00
V2	rx_frame_err	uart_intr	7.833m	238.491ms	50	50	100.00
V2	rx_break_err	uart_intr	7.833m	238.491ms	50	50	100.00
V2	rx_timeout	uart_intr	7.833m	238.491ms	50	50	100.00
V2	perf	uart_perf	29.229m	31.821ms	50	50	100.00
V2	sys_loopback	uart_loopback	26.570s	12.982ms	50	50	100.00
V2	line_loopback	uart_loopback	26.570s	12.982ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.810m	61.608ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.290m	94.388ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	33.390s	6.387ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.057m	6.717ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	21.453m	147.749ms	50	50	100.00
V2	stress_all	uart_stress_all	47.720m	270.935ms	50	50	100.00
V2	alert_test	uart_alert_test	0.620s	25.007us	50	50	100.00
V2	intr_test	uart_intr_test	0.660s	14.748us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.280s	83.509us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.280s	83.509us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.600s	50.279us	5	5	100.00
		uart_csr_rw	0.650s	199.906us	20	20	100.00
		uart_csr_aliasing	0.760s	17.857us	5	5	100.00
		uart_same_csr_outstanding	0.760s	126.803us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.600s	50.279us	5	5	100.00
		uart_csr_rw	0.650s	199.906us	20	20	100.00
		uart_csr_aliasing	0.760s	17.857us	5	5	100.00
		uart_same_csr_outstanding	0.760s	126.803us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	0.850s	58.699us	5	5	100.00
		uart_tl_intg_err	1.440s	467.546us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.440s	467.546us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.362m	8.052ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1319	1320	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	18	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.10	99.10	97.65	100.00	--	98.38	100.00	99.48

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:771) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.

has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

35.uart_stress_all_with_rand_reset.19406315332455037820646089138660554756072173418321709303545310323993909196815
Line 321, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/35.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3342863904 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3342863904 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 7/10
  UVM_INFO @ 3342945536 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 7/10