UART Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: `d09e282b26`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	30.260s	6.285ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.920s	1.031ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	42.145us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.430s	464.932us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.680s	22.438us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.170s	43.344us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	42.145us	20	20	100.00
		uart_csr_aliasing	0.680s	22.438us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.461m	123.331ms	50	50	100.00
V2	parity	uart_smoke	30.260s	6.285ms	50	50	100.00
		uart_tx_rx	3.461m	123.331ms	50	50	100.00
V2	parity_error	uart_intr	6.620m	273.869ms	50	50	100.00
		uart_rx_parity_err	14.414m	103.576ms	50	50	100.00
V2	watermark	uart_tx_rx	3.461m	123.331ms	50	50	100.00
		uart_intr	6.620m	273.869ms	50	50	100.00
V2	fifo_full	uart_fifo_full	4.817m	203.475ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	8.043m	252.303ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	12.393m	243.616ms	300	300	100.00
V2	rx_frame_err	uart_intr	6.620m	273.869ms	50	50	100.00
V2	rx_break_err	uart_intr	6.620m	273.869ms	50	50	100.00
V2	rx_timeout	uart_intr	6.620m	273.869ms	50	50	100.00
V2	perf	uart_perf	25.367m	27.234ms	50	50	100.00
V2	sys_loopback	uart_loopback	20.800s	6.843ms	50	50	100.00
V2	line_loopback	uart_loopback	20.800s	6.843ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.851m	123.201ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.134m	50.587ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	32.710s	12.323ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.081m	6.995ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	21.629m	168.114ms	50	50	100.00
V2	stress_all	uart_stress_all	38.284m	239.617ms	50	50	100.00
V2	alert_test	uart_alert_test	0.620s	16.957us	50	50	100.00
V2	intr_test	uart_intr_test	0.600s	12.335us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.320s	257.704us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.320s	257.704us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.920s	1.031ms	5	5	100.00
		uart_csr_rw	0.650s	42.145us	20	20	100.00
		uart_csr_aliasing	0.680s	22.438us	5	5	100.00
		uart_same_csr_outstanding	0.770s	90.505us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.920s	1.031ms	5	5	100.00
		uart_csr_rw	0.650s	42.145us	20	20	100.00
		uart_csr_aliasing	0.680s	22.438us	5	5	100.00
		uart_same_csr_outstanding	0.770s	90.505us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	0.890s	412.681us	5	5	100.00
		uart_tl_intg_err	1.350s	86.411us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.350s	86.411us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.865m	6.096ms	96	100	96.00
V3		TOTAL			96	100	96.00
		TOTAL			1316	1320	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	18	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.10	99.10	97.65	100.00	--	98.38	100.00	99.50

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:771) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.

has 4 failures:

Test uart_stress_all_with_rand_reset has 4 failures.

7.uart_stress_all_with_rand_reset.48921220315783411214621107458924124691390854355551235395503209008000482373838
Line 269, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 878648352 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 878648352 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 878688352 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 2/10

25.uart_stress_all_with_rand_reset.564875844183750292463252317990721570570166174909529944904317468053921598554
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  13622002 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  13622002 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @  13747003 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 1/10

... and 2 more failures.