UART Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	33.340s	6.012ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.640s	53.508us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.660s	18.055us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.350s	171.802us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.800s	32.905us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.400s	52.926us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.660s	18.055us	20	20	100.00
		uart_csr_aliasing	0.800s	32.905us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	5.216m	111.478ms	50	50	100.00
V2	parity	uart_smoke	33.340s	6.012ms	50	50	100.00
		uart_tx_rx	5.216m	111.478ms	50	50	100.00
V2	parity_error	uart_intr	20.883m	804.270ms	50	50	100.00
		uart_rx_parity_err	5.080m	73.104ms	50	50	100.00
V2	watermark	uart_tx_rx	5.216m	111.478ms	50	50	100.00
		uart_intr	20.883m	804.270ms	50	50	100.00
V2	fifo_full	uart_fifo_full	15.952m	281.139ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	7.454m	216.349ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	15.870m	156.683ms	300	300	100.00
V2	rx_frame_err	uart_intr	20.883m	804.270ms	50	50	100.00
V2	rx_break_err	uart_intr	20.883m	804.270ms	50	50	100.00
V2	rx_timeout	uart_intr	20.883m	804.270ms	50	50	100.00
V2	perf	uart_perf	24.036m	24.159ms	50	50	100.00
V2	sys_loopback	uart_loopback	25.310s	11.170ms	50	50	100.00
V2	line_loopback	uart_loopback	25.310s	11.170ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.950m	116.591ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.784m	84.035ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	33.190s	12.264ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.097m	6.692ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	28.492m	169.943ms	50	50	100.00
V2	stress_all	uart_stress_all	40.671m	150.986ms	50	50	100.00
V2	alert_test	uart_alert_test	0.610s	23.473us	50	50	100.00
V2	intr_test	uart_intr_test	0.620s	14.499us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.670s	160.431us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.670s	160.431us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.640s	53.508us	5	5	100.00
		uart_csr_rw	0.660s	18.055us	20	20	100.00
		uart_csr_aliasing	0.800s	32.905us	5	5	100.00
		uart_same_csr_outstanding	0.840s	114.575us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.640s	53.508us	5	5	100.00
		uart_csr_rw	0.660s	18.055us	20	20	100.00
		uart_csr_aliasing	0.800s	32.905us	5	5	100.00
		uart_same_csr_outstanding	0.840s	114.575us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	0.940s	307.735us	5	5	100.00
		uart_tl_intg_err	1.380s	86.463us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.380s	86.463us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.972m	61.936ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1318	1320	99.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	18	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.57

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

23.uart_stress_all_with_rand_reset.7494588693408265532318816805721457403154153482760036026173124621543971657365
Line 333, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/23.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10148703597 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 10285496358 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/601
  UVM_INFO @ 10766333538 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/601
  UVM_INFO @ 11151711621 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/601
  UVM_INFO @ 11458255740 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/601

UVM_ERROR (cip_base_vseq.sv:771) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

77.uart_stress_all_with_rand_reset.51886604802237808916723183544874444896143320855221502251323734006948274968885
Line 321, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4751938021 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4751938021 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 6/10
  UVM_INFO @ 4752078021 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 6/10