UART Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	28.800s	5.544ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.640s	156.223us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.670s	18.390us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.480s	1.381ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.770s	128.234us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.290s	56.267us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.670s	18.390us	20	20	100.00
		uart_csr_aliasing	0.770s	128.234us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.888m	142.516ms	50	50	100.00
V2	parity	uart_smoke	28.800s	5.544ms	50	50	100.00
		uart_tx_rx	4.888m	142.516ms	50	50	100.00
V2	parity_error	uart_intr	7.761m	208.513ms	50	50	100.00
		uart_rx_parity_err	4.892m	115.547ms	50	50	100.00
V2	watermark	uart_tx_rx	4.888m	142.516ms	50	50	100.00
		uart_intr	7.761m	208.513ms	50	50	100.00
V2	fifo_full	uart_fifo_full	8.032m	219.383ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.809m	94.999ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	11.085m	135.291ms	299	300	99.67
V2	rx_frame_err	uart_intr	7.761m	208.513ms	50	50	100.00
V2	rx_break_err	uart_intr	7.761m	208.513ms	50	50	100.00
V2	rx_timeout	uart_intr	7.761m	208.513ms	50	50	100.00
V2	perf	uart_perf	24.003m	23.930ms	50	50	100.00
V2	sys_loopback	uart_loopback	39.420s	9.563ms	50	50	100.00
V2	line_loopback	uart_loopback	39.420s	9.563ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	8.558m	206.862ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.529m	55.067ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	47.650s	6.958ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.125m	7.250ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	20.195m	193.344ms	49	50	98.00
V2	stress_all	uart_stress_all	24.062m	392.784ms	48	50	96.00
V2	alert_test	uart_alert_test	0.630s	12.936us	50	50	100.00
V2	intr_test	uart_intr_test	0.650s	22.642us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.540s	131.863us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.540s	131.863us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.640s	156.223us	5	5	100.00
		uart_csr_rw	0.670s	18.390us	20	20	100.00
		uart_csr_aliasing	0.770s	128.234us	5	5	100.00
		uart_same_csr_outstanding	0.790s	59.155us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.640s	156.223us	5	5	100.00
		uart_csr_rw	0.670s	18.390us	20	20	100.00
		uart_csr_aliasing	0.770s	128.234us	5	5	100.00
		uart_same_csr_outstanding	0.790s	59.155us	20	20	100.00
V2		TOTAL			1086	1090	99.63
V2S	tl_intg_err	uart_sec_cm	0.860s	183.954us	5	5	100.00
		uart_tl_intg_err	1.420s	415.348us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.420s	415.348us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.402m	4.753ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1315	1320	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	15	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.59

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 3 failures:

Test uart_stress_all has 2 failures.

5.uart_stress_all.100883858664062461591225965369789128312851031063841584120928961647846631241824
Line 327, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/5.uart_stress_all/latest/run.log

  UVM_ERROR @ 110786577213 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 111450332523 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/10
  UVM_INFO @ 111495624552 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/10
  UVM_INFO @ 111582450433 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 5/10
  UVM_INFO @ 111588541962 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 6/10

16.uart_stress_all.68441810198215418455448114285548246135458174651152196778966104173009067130544
Line 267, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/16.uart_stress_all/latest/run.log

  UVM_ERROR @ 161114313587 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 184192913676 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/8
  UVM_INFO @ 204539649291 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/8
  UVM_INFO @ 209325889164 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/8
  UVM_INFO @ 219666729050 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 4/8

Test uart_fifo_reset has 1 failures.

79.uart_fifo_reset.42850780135681133799693259998765829229307353168979597959832998772393795050782
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/79.uart_fifo_reset/latest/run.log

  UVM_ERROR @   3535110 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 4206975110 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/6
  UVM_INFO @ 12089895110 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/6
  UVM_INFO @ 23015095110 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/6
  UVM_INFO @ 23815375110 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/6

UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

Test uart_long_xfer_wo_dly has 1 failures.

29.uart_long_xfer_wo_dly.9907962198652591640479474103767477571723670485122535085288287339790181234024
Line 249, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/29.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @ 10674135099 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 10827489267 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 11001431835 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 11349964035 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 11503318203 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1

UVM_ERROR (cip_base_vseq.sv:771) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

99.uart_stress_all_with_rand_reset.87303367550129650636136281376816427987345584743334193692940353562653017220254
Line 273, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 625852917 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 625852917 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 3/5
  UVM_INFO @ 625905002 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 3/5