UART Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: `f1535c5540`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	50.890s	11.053ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.870s	1.098ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.640s	36.049us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.410s	172.034us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.830s	93.729us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.490s	32.470us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	36.049us	20	20	100.00
		uart_csr_aliasing	0.830s	93.729us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.736m	180.167ms	50	50	100.00
V2	parity	uart_smoke	50.890s	11.053ms	50	50	100.00
		uart_tx_rx	4.736m	180.167ms	50	50	100.00
V2	parity_error	uart_intr	16.077m	526.489ms	50	50	100.00
		uart_rx_parity_err	3.510m	124.349ms	50	50	100.00
V2	watermark	uart_tx_rx	4.736m	180.167ms	50	50	100.00
		uart_intr	16.077m	526.489ms	50	50	100.00
V2	fifo_full	uart_fifo_full	11.490m	216.869ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.518m	246.314ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	13.188m	138.674ms	300	300	100.00
V2	rx_frame_err	uart_intr	16.077m	526.489ms	50	50	100.00
V2	rx_break_err	uart_intr	16.077m	526.489ms	50	50	100.00
V2	rx_timeout	uart_intr	16.077m	526.489ms	50	50	100.00
V2	perf	uart_perf	19.113m	21.928ms	50	50	100.00
V2	sys_loopback	uart_loopback	19.140s	10.539ms	50	50	100.00
V2	line_loopback	uart_loopback	19.140s	10.539ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	6.208m	168.987ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.136m	42.203ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	30.790s	6.256ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.125m	7.481ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	23.431m	153.783ms	50	50	100.00
V2	stress_all	uart_stress_all	27.981m	72.345ms	49	50	98.00
V2	alert_test	uart_alert_test	0.650s	41.029us	50	50	100.00
V2	intr_test	uart_intr_test	0.620s	43.450us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.390s	134.718us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.390s	134.718us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.870s	1.098ms	5	5	100.00
		uart_csr_rw	0.640s	36.049us	20	20	100.00
		uart_csr_aliasing	0.830s	93.729us	5	5	100.00
		uart_same_csr_outstanding	0.800s	32.444us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.870s	1.098ms	5	5	100.00
		uart_csr_rw	0.640s	36.049us	20	20	100.00
		uart_csr_aliasing	0.830s	93.729us	5	5	100.00
		uart_same_csr_outstanding	0.800s	32.444us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	0.880s	81.257us	5	5	100.00
		uart_tl_intg_err	1.350s	411.164us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.350s	411.164us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.889m	11.381ms	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1319	1320	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.10	97.65	100.00	--	98.38	100.00	99.41

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

Test uart_stress_all has 1 failures.

7.uart_stress_all.33585931203430039649097467421530864852981687830845544367603521022997039665822
Line 281, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_stress_all/latest/run.log

  UVM_ERROR @ 297520362659 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_ERROR @ 297664893227 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_INFO @ 297996778235 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/6
  UVM_INFO @ 298010072459 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 5/6
  UVM_INFO @ 299222376275 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 6/6