UART Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: `e45ccd274a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	37.720s	11.618ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.230s	1.049ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.630s	50.125us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.230s	221.727us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.820s	112.868us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.330s	54.692us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.630s	50.125us	20	20	100.00
		uart_csr_aliasing	0.820s	112.868us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.646m	136.085ms	50	50	100.00
V2	parity	uart_smoke	37.720s	11.618ms	50	50	100.00
		uart_tx_rx	3.646m	136.085ms	50	50	100.00
V2	parity_error	uart_intr	16.356m	606.923ms	49	50	98.00
		uart_rx_parity_err	21.648m	334.999ms	50	50	100.00
V2	watermark	uart_tx_rx	3.646m	136.085ms	50	50	100.00
		uart_intr	16.356m	606.923ms	49	50	98.00
V2	fifo_full	uart_fifo_full	9.813m	143.978ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.040m	160.064ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	10.500m	227.223ms	300	300	100.00
V2	rx_frame_err	uart_intr	16.356m	606.923ms	49	50	98.00
V2	rx_break_err	uart_intr	16.356m	606.923ms	49	50	98.00
V2	rx_timeout	uart_intr	16.356m	606.923ms	49	50	98.00
V2	perf	uart_perf	25.551m	32.105ms	50	50	100.00
V2	sys_loopback	uart_loopback	18.930s	9.972ms	50	50	100.00
V2	line_loopback	uart_loopback	18.930s	9.972ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.907m	133.253ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.391m	51.707ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	43.960s	12.775ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.060m	6.689ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	16.776m	103.926ms	48	50	96.00
V2	stress_all	uart_stress_all	26.751m	482.951ms	50	50	100.00
V2	alert_test	uart_alert_test	0.690s	22.134us	50	50	100.00
V2	intr_test	uart_intr_test	0.660s	14.911us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.650s	701.675us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.650s	701.675us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.230s	1.049ms	5	5	100.00
		uart_csr_rw	0.630s	50.125us	20	20	100.00
		uart_csr_aliasing	0.820s	112.868us	5	5	100.00
		uart_same_csr_outstanding	0.780s	33.968us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.230s	1.049ms	5	5	100.00
		uart_csr_rw	0.630s	50.125us	20	20	100.00
		uart_csr_aliasing	0.820s	112.868us	5	5	100.00
		uart_same_csr_outstanding	0.780s	33.968us	20	20	100.00
V2		TOTAL			1087	1090	99.72
V2S	tl_intg_err	uart_sec_cm	0.900s	59.835us	5	5	100.00
		uart_tl_intg_err	1.340s	226.005us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.340s	226.005us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.685m	5.263ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1315	1320	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.10	97.65	100.00	--	98.38	100.00	99.44

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 2 failures:

Test uart_intr has 1 failures.

5.uart_intr.97583890168682741549322238286048032319670845041033856098046183615908582338973
Line 283, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/5.uart_intr/latest/run.log

  UVM_ERROR @ 86927162379 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 87024662379 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr
  UVM_INFO @ 87216482379 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 2/2
  UVM_INFO @ 87228302379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

Test uart_long_xfer_wo_dly has 1 failures.

38.uart_long_xfer_wo_dly.85762168996356266385665745592857688779557774383430897356296201147238858853535
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/38.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @    987503 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 1706887503 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/10
  UVM_INFO @ 2799957503 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/10
  UVM_INFO @ 11441117503 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/10
  UVM_INFO @ 17861587503 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 4/10

UVM_ERROR (cip_base_vseq.sv:867) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

14.uart_stress_all_with_rand_reset.110707515974411712320258233344589737764542141520830234282010138316617461413006
Line 294, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1383802082 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1383802214 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1383802214 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 4/10
  UVM_INFO @ 1383812082 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1

50.uart_stress_all_with_rand_reset.69748994878545721091388513033611977641538342451005492263681654758891393046011
Line 374, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/50.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3579805250 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 3579811239 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3579811239 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 10/10
  UVM_INFO @ 3579815667 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1

UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

Test uart_long_xfer_wo_dly has 1 failures.

42.uart_long_xfer_wo_dly.113054698418816762832670806334118915517068036203028845573412228974253474443747
Line 253, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/42.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @ 131675788255 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_INFO @ 132685855159 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 6/9
  UVM_INFO @ 160506371839 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 7/9
  UVM_INFO @ 170075624863 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 8/9
  UVM_INFO @ 175557021655 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 9/9