UART Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: `34b8fc33e3`

Branch: earlgrey_1_0_0_2024_08_20_RC0

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	46.560s	6.068ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.850s	12.756us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.930s	16.880us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.430s	1.383ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	1.140s	18.875us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.340s	172.968us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.930s	16.880us	20	20	100.00
		uart_csr_aliasing	1.140s	18.875us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.665m	91.303ms	50	50	100.00
V2	parity	uart_smoke	46.560s	6.068ms	50	50	100.00
		uart_tx_rx	4.665m	91.303ms	50	50	100.00
V2	parity_error	uart_intr	9.491m	234.138ms	48	50	96.00
		uart_rx_parity_err	5.844m	133.463ms	50	50	100.00
V2	watermark	uart_tx_rx	4.665m	91.303ms	50	50	100.00
		uart_intr	9.491m	234.138ms	48	50	96.00
V2	fifo_full	uart_fifo_full	6.402m	170.138ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	12.508m	111.581ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	8.831m	149.251ms	300	300	100.00
V2	rx_frame_err	uart_intr	9.491m	234.138ms	48	50	96.00
V2	rx_break_err	uart_intr	9.491m	234.138ms	48	50	96.00
V2	rx_timeout	uart_intr	9.491m	234.138ms	48	50	96.00
V2	perf	uart_perf	24.720m	29.062ms	50	50	100.00
V2	sys_loopback	uart_loopback	44.510s	12.191ms	50	50	100.00
V2	line_loopback	uart_loopback	44.510s	12.191ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.155m	116.134ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.826m	49.908ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	35.910s	7.099ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.336m	6.332ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	23.210m	154.128ms	50	50	100.00
V2	stress_all	uart_stress_all	26.124m	149.189ms	49	50	98.00
V2	alert_test	uart_alert_test	0.850s	14.380us	50	50	100.00
V2	intr_test	uart_intr_test	0.850s	33.537us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.240s	539.894us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.240s	539.894us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.850s	12.756us	5	5	100.00
		uart_csr_rw	0.930s	16.880us	20	20	100.00
		uart_csr_aliasing	1.140s	18.875us	5	5	100.00
		uart_same_csr_outstanding	1.130s	140.510us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.850s	12.756us	5	5	100.00
		uart_csr_rw	0.930s	16.880us	20	20	100.00
		uart_csr_aliasing	1.140s	18.875us	5	5	100.00
		uart_same_csr_outstanding	1.130s	140.510us	20	20	100.00
V2		TOTAL			1087	1090	99.72
V2S	tl_intg_err	uart_sec_cm	1.240s	239.401us	5	5	100.00
		uart_tl_intg_err	1.990s	396.402us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.990s	396.402us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.974m	4.357ms	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1317	1320	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.10	97.65	100.00	--	98.38	100.00	99.55

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty

has 3 failures:

Test uart_intr has 2 failures.

2.uart_intr.101277829230572242483331430609225547683765332444635320250695408699314053685151
Line 103, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_intr/latest/run.log

  UVM_ERROR @ 17786514616 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 17871402749 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxWatermark
  UVM_INFO @ 19333293278 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr

28.uart_intr.13147543662657467428564768914502029434259693112199242571289257422376658616831
Line 77, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/28.uart_intr/latest/run.log

  UVM_ERROR @ 8773078847 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 8865812799 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxWatermark
  UVM_INFO @ 9039505287 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/4
  UVM_INFO @ 9039586919 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

Test uart_stress_all has 1 failures.

3.uart_stress_all.71031226117913207288849571146494615858477621711846589073329672199903120860089
Line 201, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_stress_all/latest/run.log

  UVM_ERROR @ 366197572696 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 366274573312 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxEmpty
  UVM_INFO @ 366430837720 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxDone