UART Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: `0825c81be0`

Branch: os_regression_2024_08_22

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	21.440s	5.820ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.550s	58.462us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.600s	44.279us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.420s	255.083us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.750s	238.050us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.140s	52.897us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.600s	44.279us	20	20	100.00
		uart_csr_aliasing	0.750s	238.050us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	2.929m	94.615ms	50	50	100.00
V2	parity	uart_smoke	21.440s	5.820ms	50	50	100.00
		uart_tx_rx	2.929m	94.615ms	50	50	100.00
V2	parity_error	uart_intr	8.846m	325.974ms	49	50	98.00
		uart_rx_parity_err	9.126m	218.000ms	50	50	100.00
V2	watermark	uart_tx_rx	2.929m	94.615ms	50	50	100.00
		uart_intr	8.846m	325.974ms	49	50	98.00
V2	fifo_full	uart_fifo_full	13.753m	284.820ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	3.603m	165.210ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.293m	119.797ms	300	300	100.00
V2	rx_frame_err	uart_intr	8.846m	325.974ms	49	50	98.00
V2	rx_break_err	uart_intr	8.846m	325.974ms	49	50	98.00
V2	rx_timeout	uart_intr	8.846m	325.974ms	49	50	98.00
V2	perf	uart_perf	21.847m	24.706ms	50	50	100.00
V2	sys_loopback	uart_loopback	23.920s	11.951ms	50	50	100.00
V2	line_loopback	uart_loopback	23.920s	11.951ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.561m	131.700ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.352m	85.432ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	23.640s	6.569ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	58.670s	7.575ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	13.464m	93.990ms	50	50	100.00
V2	stress_all	uart_stress_all	25.863m	225.611ms	49	50	98.00
V2	alert_test	uart_alert_test	0.530s	43.201us	50	50	100.00
V2	intr_test	uart_intr_test	0.590s	10.979us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.260s	150.851us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.260s	150.851us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.550s	58.462us	5	5	100.00
		uart_csr_rw	0.600s	44.279us	20	20	100.00
		uart_csr_aliasing	0.750s	238.050us	5	5	100.00
		uart_same_csr_outstanding	0.700s	20.561us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.550s	58.462us	5	5	100.00
		uart_csr_rw	0.600s	44.279us	20	20	100.00
		uart_csr_aliasing	0.750s	238.050us	5	5	100.00
		uart_same_csr_outstanding	0.700s	20.561us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	0.800s	238.035us	5	5	100.00
		uart_tl_intg_err	1.280s	93.053us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.280s	93.053us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.565m	17.578ms	97	100	97.00
V3		TOTAL			97	100	97.00
		TOTAL			1315	1320	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.10	99.10	97.65	100.00	--	98.38	100.00	99.48

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 3 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

4.uart_stress_all_with_rand_reset.63536969957419776529833748741904148471310033617605788376010133044231294895365
Line 114, in log /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4509573724 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 4509573724 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 4534840387 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 5/10
  UVM_INFO @ 4534923721 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

Test uart_intr has 1 failures.

25.uart_intr.42164574042410824273736445647097919934301208289398469974166758543958500963059
Line 86, in log /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/25.uart_intr/latest/run.log

  UVM_ERROR @ 23753382027 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 23839316291 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxParityErr
  UVM_INFO @ 23925850537 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxDone

Test uart_stress_all has 1 failures.

47.uart_stress_all.43129615744849416558268128647172022696349155439855239633377966462803819882310
Line 104, in log /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/47.uart_stress_all/latest/run.log

  UVM_ERROR @ 149397410480 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 150417973744 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr
  UVM_INFO @ 169169068632 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxTimeout

UVM_ERROR (cip_base_vseq.sv:867) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

1.uart_stress_all_with_rand_reset.6240113833777013724679782339228137365695652529193287695756096377604257345578
Line 164, in log /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11041083653 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 11041083783 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 11041083783 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 9/10
  UVM_INFO @ 11041122115 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2

5.uart_stress_all_with_rand_reset.81088766938634920435145979903174362871126509988209046001390142143046734324446
Line 207, in log /workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9310876640 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 9310887505 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 9310887505 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 10/10
  UVM_INFO @ 9310896640 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1