UART Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: `e733a8ef8a`

Branch: os_regression_2024_08_24

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	38.580s	5.320ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.890s	25.820us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.940s	14.495us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.550s	688.922us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	1.160s	262.518us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.130s	231.364us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.940s	14.495us	20	20	100.00
		uart_csr_aliasing	1.160s	262.518us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	6.565m	100.758ms	50	50	100.00
V2	parity	uart_smoke	38.580s	5.320ms	50	50	100.00
		uart_tx_rx	6.565m	100.758ms	50	50	100.00
V2	parity_error	uart_intr	17.404m	334.604ms	49	50	98.00
		uart_rx_parity_err	11.373m	258.405ms	50	50	100.00
V2	watermark	uart_tx_rx	6.565m	100.758ms	50	50	100.00
		uart_intr	17.404m	334.604ms	49	50	98.00
V2	fifo_full	uart_fifo_full	11.939m	148.629ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	17.242m	138.171ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.288m	245.386ms	299	300	99.67
V2	rx_frame_err	uart_intr	17.404m	334.604ms	49	50	98.00
V2	rx_break_err	uart_intr	17.404m	334.604ms	49	50	98.00
V2	rx_timeout	uart_intr	17.404m	334.604ms	49	50	98.00
V2	perf	uart_perf	37.322m	32.600ms	50	50	100.00
V2	sys_loopback	uart_loopback	48.300s	13.313ms	50	50	100.00
V2	line_loopback	uart_loopback	48.300s	13.313ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	10.588m	137.150ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.653m	81.109ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	58.210s	6.544ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.615m	8.019ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	31.179m	139.699ms	50	50	100.00
V2	stress_all	uart_stress_all	56.403m	375.819ms	50	50	100.00
V2	alert_test	uart_alert_test	0.880s	14.621us	50	50	100.00
V2	intr_test	uart_intr_test	0.880s	15.080us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.260s	89.840us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.260s	89.840us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.890s	25.820us	5	5	100.00
		uart_csr_rw	0.940s	14.495us	20	20	100.00
		uart_csr_aliasing	1.160s	262.518us	5	5	100.00
		uart_same_csr_outstanding	1.130s	141.724us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.890s	25.820us	5	5	100.00
		uart_csr_rw	0.940s	14.495us	20	20	100.00
		uart_csr_aliasing	1.160s	262.518us	5	5	100.00
		uart_same_csr_outstanding	1.130s	141.724us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	1.330s	65.514us	5	5	100.00
		uart_tl_intg_err	2.350s	249.877us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.350s	249.877us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.444m	20.371ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1316	1320	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.62

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 3 failures:

Test uart_intr has 1 failures.

20.uart_intr.65674821183451462759009865854655291096157550333329752943992377891708184754119
Line 77, in log /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/20.uart_intr/latest/run.log

  UVM_ERROR @ 10097680918 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 10184200367 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr
  UVM_INFO @ 10714275219 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2
  UVM_INFO @ 10714400217 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

Test uart_stress_all_with_rand_reset has 1 failures.

28.uart_stress_all_with_rand_reset.69669536854425398365727511478241028277407809363807992367272048647369770433469
Line 83, in log /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/28.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6160982825 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 6513444011 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/369
  UVM_INFO @ 7107812492 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/5
  UVM_INFO @ 7378827761 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/369
  UVM_INFO @ 7966519481 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/369

Test uart_fifo_reset has 1 failures.

286.uart_fifo_reset.112828330672616705713462603051736308200505303205062483494844478699521933284532
Line 61, in log /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/286.uart_fifo_reset/latest/run.log

  UVM_ERROR @   1567588 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 1825667624 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/10
  UVM_INFO @ 31647548977 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/10
  UVM_INFO @ 31969861374 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/10
  UVM_INFO @ 33300987302 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/10

UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

83.uart_stress_all_with_rand_reset.15678968669704003277754160609542813559613881628571526591991841062359082775340
Line 175, in log /workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/83.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15980631789 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_INFO @ 16059279477 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/893
  UVM_ERROR @ 16191868773 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_INFO @ 16258516365 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/9
  UVM_INFO @ 16364811333 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/893