UART Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: `4674f625b3`

Branch: os_regression_2024_08_26

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.021m	10.594ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.900s	28.894us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.940s	18.762us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.210s	129.826us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	1.160s	128.930us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.450s	116.940us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.940s	18.762us	20	20	100.00
		uart_csr_aliasing	1.160s	128.930us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	6.940m	131.412ms	50	50	100.00
V2	parity	uart_smoke	1.021m	10.594ms	50	50	100.00
		uart_tx_rx	6.940m	131.412ms	50	50	100.00
V2	parity_error	uart_intr	14.243m	514.573ms	50	50	100.00
		uart_rx_parity_err	13.560m	137.694ms	50	50	100.00
V2	watermark	uart_tx_rx	6.940m	131.412ms	50	50	100.00
		uart_intr	14.243m	514.573ms	50	50	100.00
V2	fifo_full	uart_fifo_full	9.039m	192.310ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	8.673m	86.462ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	11.738m	189.055ms	298	300	99.33
V2	rx_frame_err	uart_intr	14.243m	514.573ms	50	50	100.00
V2	rx_break_err	uart_intr	14.243m	514.573ms	50	50	100.00
V2	rx_timeout	uart_intr	14.243m	514.573ms	50	50	100.00
V2	perf	uart_perf	25.764m	26.781ms	50	50	100.00
V2	sys_loopback	uart_loopback	47.010s	10.347ms	50	50	100.00
V2	line_loopback	uart_loopback	47.010s	10.347ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.380m	84.577ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.341m	27.736ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	26.050s	6.632ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.341m	7.149ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	16.966m	121.322ms	50	50	100.00
V2	stress_all	uart_stress_all	32.862m	205.876ms	50	50	100.00
V2	alert_test	uart_alert_test	0.870s	27.121us	50	50	100.00
V2	intr_test	uart_intr_test	0.870s	14.814us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.750s	488.192us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.750s	488.192us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.900s	28.894us	5	5	100.00
		uart_csr_rw	0.940s	18.762us	20	20	100.00
		uart_csr_aliasing	1.160s	128.930us	5	5	100.00
		uart_same_csr_outstanding	1.040s	74.346us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.900s	28.894us	5	5	100.00
		uart_csr_rw	0.940s	18.762us	20	20	100.00
		uart_csr_aliasing	1.160s	128.930us	5	5	100.00
		uart_same_csr_outstanding	1.040s	74.346us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	1.740s	781.128us	5	5	100.00
		uart_tl_intg_err	1.900s	276.059us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.900s	276.059us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.434m	13.697ms	95	100	95.00
V3		TOTAL			95	100	95.00
		TOTAL			1313	1320	99.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.10	99.10	97.65	100.00	--	98.38	100.00	99.50

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:771) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:

Test uart_stress_all_with_rand_reset has 3 failures.

55.uart_stress_all_with_rand_reset.51771070254948557225097423349530887538112539594215706235761097051601963426312
Line 128, in log /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/55.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5925085333 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 5925085333 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 5/5
  UVM_INFO @ 5925335335 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 5/5

56.uart_stress_all_with_rand_reset.11461950018539811080792188394003514642252898571614842340992593506290286830950
Line 126, in log /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/56.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6536074883 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 6536074883 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 6/10
  UVM_INFO @ 6536074883 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/10
  UVM_INFO @ 6536324885 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:867) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

25.uart_stress_all_with_rand_reset.15526014369402751643520497031520863080702364060836123171013583916927603412136
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 102382946 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 102389968 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 102389968 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 102392946 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1

75.uart_stress_all_with_rand_reset.42856178432017552139741168132210184745898743192734978590116549204109944553230
Line 190, in log /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3454032683 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 3454040124 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3454040124 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 8/10
  UVM_INFO @ 3454042992 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 1 failures:

Test uart_fifo_reset has 1 failures.

81.uart_fifo_reset.57401943568473041148452948179766313699922261206887267153435296413833649660602
Line 61, in log /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/81.uart_fifo_reset/latest/run.log

  UVM_ERROR @   7864381 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 8491301881 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/7
  UVM_INFO @ 57363114381 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/7
  UVM_INFO @ 62412551881 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/7
  UVM_INFO @ 146770739381 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/7

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_fifo_reset has 1 failures.
  - 207.uart_fifo_reset.7767862312825733882068469929255077767026787784613850478856704504612070423604
    Line 69, in log /workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/207.uart_fifo_reset/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```