UART Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: `a861deb3de`

Branch: os_regression_2024_08_28

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	59.950s	11.619ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.550s	15.052us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.650s	17.802us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.020s	211.377us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.670s	19.153us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.100s	172.506us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	17.802us	20	20	100.00
		uart_csr_aliasing	0.670s	19.153us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.635m	84.263ms	50	50	100.00
V2	parity	uart_smoke	59.950s	11.619ms	50	50	100.00
		uart_tx_rx	3.635m	84.263ms	50	50	100.00
V2	parity_error	uart_intr	15.628m	356.476ms	49	50	98.00
		uart_rx_parity_err	7.406m	124.269ms	50	50	100.00
V2	watermark	uart_tx_rx	3.635m	84.263ms	50	50	100.00
		uart_intr	15.628m	356.476ms	49	50	98.00
V2	fifo_full	uart_fifo_full	8.677m	146.614ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	7.358m	261.643ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.829m	93.527ms	299	300	99.67
V2	rx_frame_err	uart_intr	15.628m	356.476ms	49	50	98.00
V2	rx_break_err	uart_intr	15.628m	356.476ms	49	50	98.00
V2	rx_timeout	uart_intr	15.628m	356.476ms	49	50	98.00
V2	perf	uart_perf	34.454m	31.620ms	50	50	100.00
V2	sys_loopback	uart_loopback	51.150s	7.909ms	50	50	100.00
V2	line_loopback	uart_loopback	51.150s	7.909ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.533m	120.682ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.632m	89.995ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	1.215m	12.142ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.362m	6.401ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	31.820m	187.822ms	49	50	98.00
V2	stress_all	uart_stress_all	1.076h	312.842ms	49	50	98.00
V2	alert_test	uart_alert_test	0.860s	14.753us	50	50	100.00
V2	intr_test	uart_intr_test	0.690s	21.238us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.110s	80.937us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.110s	80.937us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.550s	15.052us	5	5	100.00
		uart_csr_rw	0.650s	17.802us	20	20	100.00
		uart_csr_aliasing	0.670s	19.153us	5	5	100.00
		uart_same_csr_outstanding	0.790s	49.094us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.550s	15.052us	5	5	100.00
		uart_csr_rw	0.650s	17.802us	20	20	100.00
		uart_csr_aliasing	0.670s	19.153us	5	5	100.00
		uart_same_csr_outstanding	0.790s	49.094us	20	20	100.00
V2		TOTAL			1086	1090	99.63
V2S	tl_intg_err	uart_sec_cm	1.360s	367.671us	5	5	100.00
		uart_tl_intg_err	1.300s	173.479us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.300s	173.479us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.616m	5.782ms	97	100	97.00
V3		TOTAL			97	100	97.00
		TOTAL			1313	1320	99.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	14	77.78
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.59

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 4 failures:

Test uart_intr has 1 failures.

12.uart_intr.33088151428648046207016458593252301816443146141197856931690926862123658087441
Line 120, in log /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/12.uart_intr/latest/run.log

  UVM_ERROR @ 51578899906 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @ 51578899906 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 51662900578 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxFrameErr
  UVM_INFO @ 51820193503 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

Test uart_long_xfer_wo_dly has 1 failures.

25.uart_long_xfer_wo_dly.89504148041482695429348596884828562962533252719025479978592393801903314927445
Line 61, in log /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/25.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @   2699998 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 4740209620 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/10
  UVM_INFO @ 7608233698 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/10
  UVM_INFO @ 21283646677 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/10
  UVM_INFO @ 22310720818 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 4/10

Test uart_stress_all has 1 failures.

33.uart_stress_all.103851827783353211150569585162033684416335564561223054567685413653088305950416
Line 71, in log /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/33.uart_stress_all/latest/run.log

  UVM_ERROR @ 25893653651 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 27488687559 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 2/8
  UVM_INFO @ 41967600685 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 3/8
  UVM_INFO @ 42529771225 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 4/8
  UVM_INFO @ 66634713551 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 5/8

Test uart_stress_all_with_rand_reset has 1 failures.

55.uart_stress_all_with_rand_reset.45755268638789075804366068268848519300460851644802268985526458752597659975191
Line 166, in log /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/55.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9809768741 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 10066010081 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/886
  UVM_INFO @ 10330007441 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/886
  UVM_INFO @ 10446006281 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/886
  UVM_INFO @ 10537639511 ps: (cip_base_vseq__tl_errors.svh:277) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/886

UVM_ERROR (cip_base_vseq.sv:771) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

38.uart_stress_all_with_rand_reset.17806977653901068119673276316090025809304170491591335288251354863232794365311
Line 183, in log /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4050258409 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4050258409 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 9/10
  UVM_INFO @ 4050340764 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 9/10

48.uart_stress_all_with_rand_reset.50288678673440428269739346951476876281658727142445942444995993876279698363936
Line 85, in log /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/48.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4027691288 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4027691288 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 4028051288 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 2/10

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_fifo_reset has 1 failures.
  - 35.uart_fifo_reset.44702184475117271977134766360761235232961219381436230203540448859986741457636
    Line 71, in log /workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/35.uart_fifo_reset/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```