UART Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke uart_smoke 46.500s 6.281ms 50 50 100.00
V1 csr_hw_reset uart_csr_hw_reset 0.890s 13.790us 5 5 100.00
V1 csr_rw uart_csr_rw 0.940s 17.985us 20 20 100.00
V1 csr_bit_bash uart_csr_bit_bash 3.430s 793.984us 5 5 100.00
V1 csr_aliasing uart_csr_aliasing 1.160s 18.406us 5 5 100.00
V1 csr_mem_rw_with_rand_reset uart_csr_mem_rw_with_rand_reset 1.990s 54.202us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr uart_csr_rw 0.940s 17.985us 20 20 100.00
uart_csr_aliasing 1.160s 18.406us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 base_random_seq uart_tx_rx 4.953m 97.375ms 50 50 100.00
V2 parity uart_smoke 46.500s 6.281ms 50 50 100.00
uart_tx_rx 4.953m 97.375ms 50 50 100.00
V2 parity_error uart_intr 9.846m 305.951ms 50 50 100.00
uart_rx_parity_err 10.339m 113.922ms 50 50 100.00
V2 watermark uart_tx_rx 4.953m 97.375ms 50 50 100.00
uart_intr 9.846m 305.951ms 50 50 100.00
V2 fifo_full uart_fifo_full 7.625m 217.880ms 50 50 100.00
V2 fifo_overflow uart_fifo_overflow 13.412m 310.561ms 50 50 100.00
V2 fifo_reset uart_fifo_reset 18.231m 144.009ms 300 300 100.00
V2 rx_frame_err uart_intr 9.846m 305.951ms 50 50 100.00
V2 rx_break_err uart_intr 9.846m 305.951ms 50 50 100.00
V2 rx_timeout uart_intr 9.846m 305.951ms 50 50 100.00
V2 perf uart_perf 22.140m 17.714ms 50 50 100.00
V2 sys_loopback uart_loopback 37.540s 8.316ms 50 50 100.00
V2 line_loopback uart_loopback 37.540s 8.316ms 50 50 100.00
V2 rx_noise_filter uart_noise_filter 7.436m 129.248ms 50 50 100.00
V2 rx_start_bit_filter uart_rx_start_bit_filter 1.399m 37.896ms 50 50 100.00
V2 tx_overide uart_tx_ovrd 58.790s 12.673ms 50 50 100.00
V2 rx_oversample uart_rx_oversample 1.253m 6.463ms 50 50 100.00
V2 long_b2b_transfer uart_long_xfer_wo_dly 22.373m 138.012ms 50 50 100.00
V2 stress_all uart_stress_all 36.263m 147.347ms 50 50 100.00
V2 alert_test uart_alert_test 0.890s 17.240us 50 50 100.00
V2 intr_test uart_intr_test 0.880s 42.194us 50 50 100.00
V2 tl_d_oob_addr_access uart_tl_errors 3.630s 344.770us 20 20 100.00
V2 tl_d_illegal_access uart_tl_errors 3.630s 344.770us 20 20 100.00
V2 tl_d_outstanding_access uart_csr_hw_reset 0.890s 13.790us 5 5 100.00
uart_csr_rw 0.940s 17.985us 20 20 100.00
uart_csr_aliasing 1.160s 18.406us 5 5 100.00
uart_same_csr_outstanding 1.300s 36.919us 20 20 100.00
V2 tl_d_partial_access uart_csr_hw_reset 0.890s 13.790us 5 5 100.00
uart_csr_rw 0.940s 17.985us 20 20 100.00
uart_csr_aliasing 1.160s 18.406us 5 5 100.00
uart_same_csr_outstanding 1.300s 36.919us 20 20 100.00
V2 TOTAL 1090 1090 100.00
V2S tl_intg_err uart_sec_cm 1.300s 60.264us 5 5 100.00
uart_tl_intg_err 2.500s 465.185us 20 20 100.00
V2S sec_cm_bus_integrity uart_tl_intg_err 2.500s 465.185us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset uart_stress_all_with_rand_reset 2.368m 8.852ms 100 100 100.00
V3 TOTAL 100 100 100.00
TOTAL 1320 1320 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 18 18 18 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.10 99.10 97.65 100.00 -- 98.38 100.00 99.48

Past Results