UART Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: `372a6306e0`

Branch: os_regression_2024_09_03

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	30.500s	6.094ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.910s	15.613us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.930s	76.302us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.590s	418.936us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	1.130s	36.634us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.840s	27.499us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.930s	76.302us	20	20	100.00
		uart_csr_aliasing	1.130s	36.634us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	7.094m	118.332ms	50	50	100.00
V2	parity	uart_smoke	30.500s	6.094ms	50	50	100.00
		uart_tx_rx	7.094m	118.332ms	50	50	100.00
V2	parity_error	uart_intr	12.524m	382.948ms	49	50	98.00
		uart_rx_parity_err	7.764m	188.294ms	50	50	100.00
V2	watermark	uart_tx_rx	7.094m	118.332ms	50	50	100.00
		uart_intr	12.524m	382.948ms	49	50	98.00
V2	fifo_full	uart_fifo_full	14.442m	303.742ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	7.470m	111.082ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	12.878m	105.212ms	299	300	99.67
V2	rx_frame_err	uart_intr	12.524m	382.948ms	49	50	98.00
V2	rx_break_err	uart_intr	12.524m	382.948ms	49	50	98.00
V2	rx_timeout	uart_intr	12.524m	382.948ms	49	50	98.00
V2	perf	uart_perf	27.285m	30.852ms	50	50	100.00
V2	sys_loopback	uart_loopback	36.600s	6.218ms	50	50	100.00
V2	line_loopback	uart_loopback	36.600s	6.218ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	8.359m	128.549ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.409m	77.812ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	39.400s	12.719ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.447m	6.093ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	19.904m	107.588ms	50	50	100.00
V2	stress_all	uart_stress_all	25.797m	292.253ms	50	50	100.00
V2	alert_test	uart_alert_test	0.870s	15.615us	50	50	100.00
V2	intr_test	uart_intr_test	0.890s	30.636us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.310s	195.946us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.310s	195.946us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.910s	15.613us	5	5	100.00
		uart_csr_rw	0.930s	76.302us	20	20	100.00
		uart_csr_aliasing	1.130s	36.634us	5	5	100.00
		uart_same_csr_outstanding	1.090s	57.636us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.910s	15.613us	5	5	100.00
		uart_csr_rw	0.930s	76.302us	20	20	100.00
		uart_csr_aliasing	1.130s	36.634us	5	5	100.00
		uart_same_csr_outstanding	1.090s	57.636us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	1.360s	110.296us	5	5	100.00
		uart_tl_intg_err	1.920s	220.741us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.920s	220.741us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.131m	10.793ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1316	1320	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.10	97.65	100.00	--	98.38	100.00	99.53

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty has 2 failures:

Test uart_intr has 1 failures.

1.uart_intr.30956218180764368304088651099331771349691615443332978874716922001498025897377
Line 124, in log /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/1.uart_intr/latest/run.log

  UVM_ERROR @ 57071136940 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 57156993396 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxParityErr
  UVM_INFO @ 57243849844 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing RxBreakErr

Test uart_fifo_reset has 1 failures.

167.uart_fifo_reset.29659653597424984024442006777427227494872150886143785758271672381090201337440
Line 61, in log /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/167.uart_fifo_reset/latest/run.log

  UVM_ERROR @   5410440 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_ERROR @   5410440 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxWatermark
  UVM_INFO @ 789296379 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/7
  UVM_INFO @ 6534650440 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/7
  UVM_INFO @ 7119370440 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/7

UVM_ERROR (cip_base_vseq.sv:867) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

81.uart_stress_all_with_rand_reset.44543142118901408780662575829104660927659181182173004261595352111669540505583
Line 169, in log /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/81.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5706703455 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 5706714806 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 5706714806 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 10/10
  UVM_INFO @ 5706723455 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2

UVM_ERROR (cip_base_vseq.sv:771) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

86.uart_stress_all_with_rand_reset.112547333276228378861512308015267718925584857482582038861046120744112081603066
Line 64, in log /workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/86.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  38438337 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  38438337 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @  38592185 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 1/5