UART Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke uart_smoke 34.000s 6.219ms 50 50 100.00
V1 csr_hw_reset uart_csr_hw_reset 0.900s 17.383us 5 5 100.00
V1 csr_rw uart_csr_rw 0.890s 22.827us 20 20 100.00
V1 csr_bit_bash uart_csr_bit_bash 3.680s 3.139ms 5 5 100.00
V1 csr_aliasing uart_csr_aliasing 1.140s 17.684us 5 5 100.00
V1 csr_mem_rw_with_rand_reset uart_csr_mem_rw_with_rand_reset 1.810s 420.424us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr uart_csr_rw 0.890s 22.827us 20 20 100.00
uart_csr_aliasing 1.140s 17.684us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 base_random_seq uart_tx_rx 5.056m 110.039ms 50 50 100.00
V2 parity uart_smoke 34.000s 6.219ms 50 50 100.00
uart_tx_rx 5.056m 110.039ms 50 50 100.00
V2 parity_error uart_intr 8.592m 523.556ms 50 50 100.00
uart_rx_parity_err 5.000m 207.748ms 50 50 100.00
V2 watermark uart_tx_rx 5.056m 110.039ms 50 50 100.00
uart_intr 8.592m 523.556ms 50 50 100.00
V2 fifo_full uart_fifo_full 12.721m 283.324ms 49 50 98.00
V2 fifo_overflow uart_fifo_overflow 5.817m 137.286ms 50 50 100.00
V2 fifo_reset uart_fifo_reset 14.655m 157.380ms 300 300 100.00
V2 rx_frame_err uart_intr 8.592m 523.556ms 50 50 100.00
V2 rx_break_err uart_intr 8.592m 523.556ms 50 50 100.00
V2 rx_timeout uart_intr 8.592m 523.556ms 50 50 100.00
V2 perf uart_perf 27.483m 29.357ms 50 50 100.00
V2 sys_loopback uart_loopback 35.960s 12.517ms 50 50 100.00
V2 line_loopback uart_loopback 35.960s 12.517ms 50 50 100.00
V2 rx_noise_filter uart_noise_filter 7.149m 162.891ms 50 50 100.00
V2 rx_start_bit_filter uart_rx_start_bit_filter 1.662m 38.826ms 50 50 100.00
V2 tx_overide uart_tx_ovrd 51.360s 12.427ms 50 50 100.00
V2 rx_oversample uart_rx_oversample 1.642m 7.719ms 50 50 100.00
V2 long_b2b_transfer uart_long_xfer_wo_dly 22.568m 146.440ms 50 50 100.00
V2 stress_all uart_stress_all 33.353m 191.117ms 50 50 100.00
V2 alert_test uart_alert_test 0.860s 17.162us 50 50 100.00
V2 intr_test uart_intr_test 0.880s 15.840us 50 50 100.00
V2 tl_d_oob_addr_access uart_tl_errors 3.310s 197.958us 20 20 100.00
V2 tl_d_illegal_access uart_tl_errors 3.310s 197.958us 20 20 100.00
V2 tl_d_outstanding_access uart_csr_hw_reset 0.900s 17.383us 5 5 100.00
uart_csr_rw 0.890s 22.827us 20 20 100.00
uart_csr_aliasing 1.140s 17.684us 5 5 100.00
uart_same_csr_outstanding 1.170s 36.250us 20 20 100.00
V2 tl_d_partial_access uart_csr_hw_reset 0.900s 17.383us 5 5 100.00
uart_csr_rw 0.890s 22.827us 20 20 100.00
uart_csr_aliasing 1.140s 17.684us 5 5 100.00
uart_same_csr_outstanding 1.170s 36.250us 20 20 100.00
V2 TOTAL 1089 1090 99.91
V2S tl_intg_err uart_sec_cm 1.300s 58.610us 5 5 100.00
uart_tl_intg_err 2.100s 145.125us 20 20 100.00
V2S sec_cm_bus_integrity uart_tl_intg_err 2.100s 145.125us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset uart_stress_all_with_rand_reset 2.286m 3.705ms 100 100 100.00
V3 TOTAL 100 100 100.00
TOTAL 1319 1320 99.92

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 18 18 17 94.44
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.09 99.10 97.65 100.00 -- 98.38 100.00 99.44

Failure Buckets

Past Results