UART Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: `25b1acbf68`

Branch: os_regression_2024_09_10

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	32.300s	5.471ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.910s	16.854us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.930s	50.216us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.870s	265.532us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	1.160s	38.109us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.510s	53.004us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.930s	50.216us	20	20	100.00
		uart_csr_aliasing	1.160s	38.109us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	8.795m	108.268ms	50	50	100.00
V2	parity	uart_smoke	32.300s	5.471ms	50	50	100.00
		uart_tx_rx	8.795m	108.268ms	50	50	100.00
V2	parity_error	uart_intr	13.573m	432.395ms	49	50	98.00
		uart_rx_parity_err	7.385m	167.433ms	50	50	100.00
V2	watermark	uart_tx_rx	8.795m	108.268ms	50	50	100.00
		uart_intr	13.573m	432.395ms	49	50	98.00
V2	fifo_full	uart_fifo_full	9.193m	219.162ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	8.005m	214.891ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	12.750m	145.532ms	300	300	100.00
V2	rx_frame_err	uart_intr	13.573m	432.395ms	49	50	98.00
V2	rx_break_err	uart_intr	13.573m	432.395ms	49	50	98.00
V2	rx_timeout	uart_intr	13.573m	432.395ms	49	50	98.00
V2	perf	uart_perf	22.188m	26.294ms	50	50	100.00
V2	sys_loopback	uart_loopback	40.460s	12.005ms	50	50	100.00
V2	line_loopback	uart_loopback	40.460s	12.005ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.004m	108.655ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.551m	30.282ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	36.730s	6.542ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.183m	5.833ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	21.423m	138.093ms	50	50	100.00
V2	stress_all	uart_stress_all	24.486m	755.829ms	50	50	100.00
V2	alert_test	uart_alert_test	0.880s	14.141us	50	50	100.00
V2	intr_test	uart_intr_test	0.900s	15.223us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.560s	795.816us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.560s	795.816us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.910s	16.854us	5	5	100.00
		uart_csr_rw	0.930s	50.216us	20	20	100.00
		uart_csr_aliasing	1.160s	38.109us	5	5	100.00
		uart_same_csr_outstanding	1.170s	210.843us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.910s	16.854us	5	5	100.00
		uart_csr_rw	0.930s	50.216us	20	20	100.00
		uart_csr_aliasing	1.160s	38.109us	5	5	100.00
		uart_same_csr_outstanding	1.170s	210.843us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	1.380s	240.751us	5	5	100.00
		uart_tl_intg_err	2.080s	96.809us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.080s	96.809us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.709m	5.646ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1318	1320	99.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.10	97.65	100.00	--	98.38	100.00	99.57

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: TxEmpty

has 2 failures:

Test uart_intr has 1 failures.

8.uart_intr.29449286762410601586634243379162571397186936639346826427189026526617627873017
Line 96, in log /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_intr/latest/run.log

  UVM_ERROR @ 49595505006 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 49681976286 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]
  Testing TxDone
  UVM_INFO @ 51852346590 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 2/4
  UVM_INFO @ 51852817182 ps: (uart_intr_vseq.sv:36) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq]

Test uart_stress_all_with_rand_reset has 1 failures.

57.uart_stress_all_with_rand_reset.60908985718121618536944921754137839845996065740944553143184370901238886310887
Line 107, in log /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/57.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2541832955 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: TxEmpty
  UVM_INFO @ 2589579073 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 5/5
  UVM_INFO @ 2589637897 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 5/5