584c3d46af| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | usbdev_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | usbdev_csr_hw_reset | 1.020s | 205.267us | 5 | 5 | 100.00 |
| V1 | csr_rw | usbdev_csr_rw | 1.060s | 87.391us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | usbdev_csr_bit_bash | 8.320s | 1.819ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | usbdev_csr_aliasing | 3.510s | 357.007us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | usbdev_csr_mem_rw_with_rand_reset | 2.640s | 101.163us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | usbdev_csr_rw | 1.060s | 87.391us | 20 | 20 | 100.00 |
| usbdev_csr_aliasing | 3.510s | 357.007us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | usbdev_mem_walk | 4.680s | 721.309us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | usbdev_mem_partial_access | 2.270s | 83.804us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | in_trans | usbdev_in_trans | 0 | 50 | 0.00 | ||
| V2 | data_toggle_clear | usbdev_data_toggle_clear | 0 | 50 | 0.00 | ||
| V2 | phy_pins_sense | usbdev_phy_pins_sense | 0 | 50 | 0.00 | ||
| V2 | av_buffer | usbdev_av_buffer | 0 | 50 | 0.00 | ||
| V2 | rx_fifo | usbdev_pkt_buffer | 0 | 50 | 0.00 | ||
| V2 | phy_config_tx_osc_test_mode | usbdev_phy_config_tx_osc_test_mode | 0 | 1 | 0.00 | ||
| V2 | phy_config_eop_single_bit_handling | usbdev_phy_config_eop_single_bit_handling | 0 | 1 | 0.00 | ||
| V2 | phy_config_pinflip | usbdev_phy_config_pinflip | 0 | 50 | 0.00 | ||
| V2 | phy_config_rand_bus_type | usbdev_phy_config_rand_bus_type | 0 | 5 | 0.00 | ||
| V2 | phy_config_rx_dp_dn | usbdev_phy_config_rx_dp_dn | 0 | 1 | 0.00 | ||
| V2 | phy_config_tx_use_d_se0 | usbdev_phy_config_tx_use_d_se0 | 0 | 1 | 0.00 | ||
| V2 | phy_config_usb_ref_disable | usbdev_phy_config_usb_ref_disable | 0 | 50 | 0.00 | ||
| V2 | max_length_out_transaction | usbdev_max_length_out_transaction | 0 | 50 | 0.00 | ||
| usbdev_stream_len_max | 0 | 50 | 0.00 | ||||
| V2 | max_length_in_transaction | usbdev_max_length_in_transaction | 0 | 50 | 0.00 | ||
| V2 | min_length_out_transaction | usbdev_min_length_out_transaction | 0 | 50 | 0.00 | ||
| V2 | min_length_in_transaction | usbdev_min_length_in_transaction | 0 | 50 | 0.00 | ||
| V2 | random_length_out_transaction | usbdev_random_length_out_transaction | 0 | 50 | 0.00 | ||
| V2 | random_length_in_transaction | usbdev_random_length_in_transaction | 0 | 50 | 0.00 | ||
| V2 | out_stall | usbdev_out_stall | 0 | 50 | 0.00 | ||
| V2 | in_stall | usbdev_in_stall | 0 | 50 | 0.00 | ||
| V2 | out_iso | usbdev_out_iso | 0 | 50 | 0.00 | ||
| V2 | in_iso | usbdev_in_iso | 0 | 50 | 0.00 | ||
| V2 | pkt_received | usbdev_pkt_received | 0 | 50 | 0.00 | ||
| V2 | pkt_sent | usbdev_pkt_sent | 0 | 50 | 0.00 | ||
| V2 | disconnected | usbdev_disconnected | 0 | 50 | 0.00 | ||
| V2 | host_lost | usbdev_host_lost | 0 | 1 | 0.00 | ||
| V2 | link_reset | usbdev_link_reset | 0 | 1 | 0.00 | ||
| V2 | link_suspend | usbdev_link_suspend | 0 | 50 | 0.00 | ||
| V2 | link_resume | usbdev_link_resume | 0 | 50 | 0.00 | ||
| V2 | av_empty | usbdev_av_empty | 0 | 5 | 0.00 | ||
| V2 | rx_full | usbdev_rx_full | 0 | 50 | 0.00 | ||
| V2 | av_overflow | usbdev_av_overflow | 0 | 5 | 0.00 | ||
| V2 | link_in_err | usbdev_link_in_err | 0 | 50 | 0.00 | ||
| V2 | rx_crc_err | usbdev_rx_crc_err | 0 | 50 | 0.00 | ||
| V2 | rx_pid_err | usbdev_rx_pid_err | 0 | 5 | 0.00 | ||
| V2 | rx_bitstuff_err | usbdev_bitstuff_err | 0 | 50 | 0.00 | ||
| V2 | link_out_err | usbdev_link_out_err | 0 | 1 | 0.00 | ||
| V2 | enable | usbdev_enable | 0 | 50 | 0.00 | ||
| V2 | resume_link_active | usbdev_resume_link_active | 0 | 20 | 0.00 | ||
| V2 | device_address | usbdev_device_address | 0 | 50 | 0.00 | ||
| V2 | invalid_data1_data0_toggle_test | usbdev_invalid_data1_data0_toggle_test | 0 | 1 | 0.00 | ||
| V2 | setup_stage | usbdev_setup_stage | 0 | 50 | 0.00 | ||
| V2 | endpoint_access | usbdev_endpoint_access | 0 | 50 | 0.00 | ||
| V2 | disable_endpoint | usbdev_disable_endpoint | 0 | 50 | 0.00 | ||
| V2 | endpoint_types | usbdev_endpoint_types | 0 | 200 | 0.00 | ||
| V2 | out_trans_nak | usbdev_out_trans_nak | 0 | 50 | 0.00 | ||
| V2 | setup_trans_ignored | usbdev_setup_trans_ignored | 0 | 50 | 0.00 | ||
| V2 | nak_trans | usbdev_nak_trans | 0 | 50 | 0.00 | ||
| V2 | stall_trans | usbdev_stall_trans | 0 | 50 | 0.00 | ||
| V2 | setup_priority_over_stall_response | usbdev_setup_priority_over_stall_response | 0 | 5 | 0.00 | ||
| V2 | stall_priority_over_nak | usbdev_stall_priority_over_nak | 0 | 50 | 0.00 | ||
| V2 | pending_in_trans | usbdev_pending_in_trans | 0 | 50 | 0.00 | ||
| V2 | streaming_test | usbdev_streaming_out | 0 | 50 | 0.00 | ||
| V2 | max_clock_error_untracked | usbdev_freq_hiclk | 0 | 5 | 0.00 | ||
| usbdev_freq_loclk | 0 | 5 | 0.00 | ||||
| V2 | max_clock_error_tracking | usbdev_freq_hiclk_max | 0 | 5 | 0.00 | ||
| usbdev_freq_loclk_max | 0 | 5 | 0.00 | ||||
| V2 | max_phase_error | usbdev_freq_phase | 0 | 5 | 0.00 | ||
| V2 | min_inter_pkt_delay | usbdev_min_inter_pkt_delay | 0 | 50 | 0.00 | ||
| V2 | max_inter_pkt_delay | usbdev_max_inter_pkt_delay | 0 | 50 | 0.00 | ||
| V2 | device_timeout_missing_host_handshake | usbdev_timeout_missing_host_handshake | 0 | 50 | 0.00 | ||
| V2 | device_timeout | usbdev_device_timeout | 0 | 50 | 0.00 | ||
| V2 | packet_buffer | usbdev_pkt_buffer | 0 | 50 | 0.00 | ||
| V2 | nak_to_out_trans_when_avbuffer_empty_rxfifo_full | usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full | 0 | 1 | 0.00 | ||
| V2 | aon_wake_resume | usbdev_aon_wake_resume | 0 | 50 | 0.00 | ||
| V2 | aon_wake_reset | usbdev_aon_wake_reset | 0 | 50 | 0.00 | ||
| V2 | aon_wake_disconnect | usbdev_aon_wake_disconnect | 0 | 50 | 0.00 | ||
| V2 | invalid_sync | usbdev_invalid_sync | 0 | 50 | 0.00 | ||
| V2 | spurious_pids_ignored | usbdev_spurious_pids_ignored | 0 | 50 | 0.00 | ||
| V2 | low_speed_traffic | usbdev_low_speed_traffic | 0 | 50 | 0.00 | ||
| V2 | rand_bus_resets | usbdev_rand_bus_resets | 0 | 10 | 0.00 | ||
| V2 | rand_disconnects | usbdev_rand_bus_disconnects | 0 | 10 | 0.00 | ||
| V2 | rand_suspends | usbdev_rand_suspends | 0 | 10 | 0.00 | ||
| V2 | max_usb_traffic | usbdev_max_non_iso_usb_traffic | 0 | 25 | 0.00 | ||
| usbdev_max_usb_traffic | 0 | 15 | 0.00 | ||||
| V2 | stress_usb_traffic | usbdev_stress_usb_traffic | 0 | 5 | 0.00 | ||
| V2 | in_packet_retraction | usbdev_iso_retraction | 0 | 50 | 0.00 | ||
| V2 | data_toggle_restore | usbdev_data_toggle_restore | 0 | 50 | 0.00 | ||
| V2 | setup_priority | usbdev_setup_priority | 0 | 5 | 0.00 | ||
| V2 | fifo_resets | usbdev_fifo_rst | 0 | 50 | 0.00 | ||
| V2 | usbdev_tx_rx_disruption | usbdev_tx_rx_disruption | 0 | 500 | 0.00 | ||
| V2 | intr_test | usbdev_intr_test | 0.840s | 151.551us | 50 | 50 | 100.00 |
| V2 | alert_test | usbdev_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | usbdev_tl_errors | 3.890s | 411.496us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | usbdev_tl_errors | 3.890s | 411.496us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | usbdev_csr_hw_reset | 1.020s | 205.267us | 5 | 5 | 100.00 |
| usbdev_csr_rw | 1.060s | 87.391us | 20 | 20 | 100.00 | ||
| usbdev_csr_aliasing | 3.510s | 357.007us | 5 | 5 | 100.00 | ||
| usbdev_same_csr_outstanding | 1.820s | 456.357us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | usbdev_csr_hw_reset | 1.020s | 205.267us | 5 | 5 | 100.00 |
| usbdev_csr_rw | 1.060s | 87.391us | 20 | 20 | 100.00 | ||
| usbdev_csr_aliasing | 3.510s | 357.007us | 5 | 5 | 100.00 | ||
| usbdev_same_csr_outstanding | 1.820s | 456.357us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 90 | 3599 | 2.50 | |||
| V2S | tl_intg_err | usbdev_sec_cm | 0 | 5 | 0.00 | ||
| usbdev_tl_intg_err | 5.380s | 1.495ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | usbdev_tl_intg_err | 5.380s | 1.495ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 20 | 25 | 80.00 | |||
| V3 | dpi_config_host | usbdev_dpi_config_host | 0 | 1 | 0.00 | ||
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | usbdev_stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| usbdev_stress_all | 0 | 50 | 0.00 | ||||
| TOTAL | 175 | 3800 | 4.61 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 2 | 2 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 85 | 85 | 3 | 3.53 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 61.28 | 65.59 | 60.85 | 86.35 | 0.00 | 71.17 | 97.77 | 47.24 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 1813 failures:
0.usbdev_aon_wake_disconnect.13924957321872322802111534361506701308610732129229857228535450094158063659647
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_disconnect/latest/run.log
2.usbdev_aon_wake_disconnect.76877378295578578721881417260464596344795306767835647218969915404447790923381
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_aon_wake_disconnect/latest/run.log
... and 21 more failures.
0.usbdev_aon_wake_resume.78554254416388278393527503653438292555596698254210216168374034586473993755664
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_resume/latest/run.log
2.usbdev_aon_wake_resume.57022780359577128601946305604225877914307679170550143170397890543794755164751
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_aon_wake_resume/latest/run.log
... and 21 more failures.
0.usbdev_av_empty.95458183683865554148538307222298826583272109313697391268993407057719009825175
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_empty/latest/run.log
2.usbdev_av_empty.95806048162269787644134714121687333771729110903120541812113167916192386638797
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_av_empty/latest/run.log
... and 1 more failures.
0.usbdev_bitstuff_err.69695652821205965439183555716668123030490730494075680695370033000523044284990
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_bitstuff_err/latest/run.log
2.usbdev_bitstuff_err.111983672340635408362827411383617311329042267485637153193238045093790190404986
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_bitstuff_err/latest/run.log
... and 21 more failures.
0.usbdev_data_toggle_restore.103799366088834238452695354349783285090467180283791523668300756346322873222509
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_data_toggle_restore/latest/run.log
2.usbdev_data_toggle_restore.21739131790947143985738774322404190668623650455181809953335404838919773129343
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_data_toggle_restore/latest/run.log
... and 21 more failures.
Job killed most likely because its dependent job failed. has 1812 failures:
0.usbdev_aon_wake_reset.58025595449925090448377781137029851110456510624397286040824313472554013687025
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_reset/latest/run.log
2.usbdev_aon_wake_reset.71814871860744467015230360595746842545605290122490036379556778905361678196540
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_aon_wake_reset/latest/run.log
... and 21 more failures.
0.usbdev_av_buffer.99078950065292281702654165488644255479735074586281145730950858009558089679059
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_buffer/latest/run.log
2.usbdev_av_buffer.77578257368631740454140027258767184466013942865313540523038724571368811287042
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_av_buffer/latest/run.log
... and 21 more failures.
0.usbdev_av_overflow.4308605123985730227060631617343371422358808091998140867452345524606580091114
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_overflow/latest/run.log
2.usbdev_av_overflow.77598878874208190816719787263431201745082892236593891958548877363241398435855
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_av_overflow/latest/run.log
... and 1 more failures.
0.usbdev_data_toggle_clear.112232672595486487260534214893499667936078114955760620637055217548200632042615
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_data_toggle_clear/latest/run.log
2.usbdev_data_toggle_clear.98429537091627514275072729315242404847775541490522440722923024947756583057087
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_data_toggle_clear/latest/run.log
... and 21 more failures.
0.usbdev_device_address.97674583201797391670041765016168481201131581631856554151164865804461290553137
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_device_address/latest/run.log
2.usbdev_device_address.45780937825307763053070377060845461669562855955051727693834196339404454573269
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_device_address/latest/run.log
... and 21 more failures.