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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.41 98.21 96.12 97.44 94.92 98.38 98.21 98.55


Total test records in report: 3901
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T3212 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/48.usbdev_iso_retraction.1981817468 Sep 24 09:32:47 AM UTC 24 Sep 24 09:34:05 AM UTC 24 7406965322 ps
T3213 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_min_inter_pkt_delay.1789344294 Sep 24 09:33:47 AM UTC 24 Sep 24 09:34:06 AM UTC 24 1825963312 ps
T3214 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_max_inter_pkt_delay.305368041 Sep 24 09:33:47 AM UTC 24 Sep 24 09:34:10 AM UTC 24 3124449938 ps
T3215 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/48.usbdev_spurious_pids_ignored.2904506798 Sep 24 09:33:16 AM UTC 24 Sep 24 09:34:15 AM UTC 24 2362724640 ps
T3216 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_iso_retraction.2515833817 Sep 24 09:33:47 AM UTC 24 Sep 24 09:34:19 AM UTC 24 4815661742 ps
T3217 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_invalid_sync.529366373 Sep 24 09:33:47 AM UTC 24 Sep 24 09:34:21 AM UTC 24 4993349428 ps
T3218 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/55.usbdev_tx_rx_disruption.453942063 Sep 24 09:35:01 AM UTC 24 Sep 24 09:35:04 AM UTC 24 600754393 ps
T3219 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_rx_crc_err.1595220462 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:24 AM UTC 24 154050501 ps
T3220 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_setup_trans_ignored.3550287906 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:24 AM UTC 24 156312699 ps
T3221 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_setup_stage.996467986 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:24 AM UTC 24 170638458 ps
T3222 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_pkt_sent.4270839151 Sep 24 09:34:21 AM UTC 24 Sep 24 09:34:24 AM UTC 24 194763430 ps
T3223 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_rx_full.3447221984 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:24 AM UTC 24 306443592 ps
T3224 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_random_length_in_transaction.2340672286 Sep 24 09:34:21 AM UTC 24 Sep 24 09:34:24 AM UTC 24 213409718 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/56.usbdev_fifo_levels.3780643438 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:04 AM UTC 24 266138372 ps
T3225 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_pkt_received.2928728112 Sep 24 09:34:21 AM UTC 24 Sep 24 09:34:24 AM UTC 24 204048534 ps
T559 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/56.usbdev_endpoint_types.4194702575 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:04 AM UTC 24 335727712 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/58.usbdev_fifo_levels.2344593705 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:04 AM UTC 24 260276967 ps
T3226 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_stall_priority_over_nak.258673804 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:24 AM UTC 24 167969685 ps
T3227 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/84.usbdev_fifo_levels.3573651966 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:40 AM UTC 24 291403910 ps
T3228 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_random_length_out_transaction.67941484 Sep 24 09:34:21 AM UTC 24 Sep 24 09:34:24 AM UTC 24 207091744 ps
T3229 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_smoke.1513862610 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:24 AM UTC 24 235134692 ps
T3230 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_alert_test.1035029142 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:24 AM UTC 24 57981289 ps
T3231 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_stall_trans.3703088078 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:24 AM UTC 24 163440307 ps
T3232 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/51.usbdev_endpoint_types.4201243500 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:24 AM UTC 24 145647111 ps
T3233 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/52.usbdev_endpoint_types.1132647351 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:24 AM UTC 24 150090570 ps
T3234 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_stream_len_max.3555714390 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:24 AM UTC 24 204363199 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/50.usbdev_fifo_levels.3907971632 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:25 AM UTC 24 286939411 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/53.usbdev_fifo_levels.2170422222 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:25 AM UTC 24 164674416 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/52.usbdev_fifo_levels.1657805261 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:25 AM UTC 24 163712008 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/51.usbdev_fifo_levels.2630382778 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:25 AM UTC 24 312326611 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/50.usbdev_endpoint_types.2981845590 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:25 AM UTC 24 244548764 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/54.usbdev_fifo_levels.3590606866 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:25 AM UTC 24 273629310 ps
T541 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/54.usbdev_endpoint_types.3979596911 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:25 AM UTC 24 349325370 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/53.usbdev_endpoint_types.954030513 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:25 AM UTC 24 528648571 ps
T3235 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/53.usbdev_tx_rx_disruption.2851981788 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:25 AM UTC 24 473085829 ps
T3236 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/52.usbdev_tx_rx_disruption.2802608932 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:25 AM UTC 24 482159159 ps
T3237 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_tx_rx_disruption.3922921943 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:25 AM UTC 24 463269466 ps
T3238 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/50.usbdev_tx_rx_disruption.2345839112 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:25 AM UTC 24 589488628 ps
T3239 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/51.usbdev_tx_rx_disruption.1267156665 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:25 AM UTC 24 587709730 ps
T3240 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_device_address.780355668 Sep 24 09:33:16 AM UTC 24 Sep 24 09:34:28 AM UTC 24 43896895478 ps
T3241 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_spurious_pids_ignored.2688203619 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:35 AM UTC 24 1890264051 ps
T3242 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_link_resume.4192218642 Sep 24 09:33:47 AM UTC 24 Sep 24 09:34:38 AM UTC 24 28798770251 ps
T3243 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_pkt_buffer.30727320 Sep 24 09:33:48 AM UTC 24 Sep 24 09:34:38 AM UTC 24 19292108309 ps
T3244 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_streaming_out.386811162 Sep 24 09:34:22 AM UTC 24 Sep 24 09:34:40 AM UTC 24 2359722392 ps
T3245 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/48.usbdev_low_speed_traffic.366341011 Sep 24 09:32:48 AM UTC 24 Sep 24 09:34:42 AM UTC 24 4510056054 ps
T547 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/55.usbdev_endpoint_types.3252976561 Sep 24 09:35:01 AM UTC 24 Sep 24 09:35:04 AM UTC 24 277649660 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/55.usbdev_fifo_levels.3637569236 Sep 24 09:35:01 AM UTC 24 Sep 24 09:35:04 AM UTC 24 269430767 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/57.usbdev_fifo_levels.2913762397 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:04 AM UTC 24 278479832 ps
T3246 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/54.usbdev_tx_rx_disruption.3021238860 Sep 24 09:35:01 AM UTC 24 Sep 24 09:35:04 AM UTC 24 543949618 ps
T3247 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/57.usbdev_tx_rx_disruption.870709772 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:04 AM UTC 24 510231008 ps
T528 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/58.usbdev_endpoint_types.662671797 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:04 AM UTC 24 565866115 ps
T3248 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/56.usbdev_tx_rx_disruption.2686244920 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:04 AM UTC 24 487147740 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/60.usbdev_fifo_levels.3305311600 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:04 AM UTC 24 279835415 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/59.usbdev_fifo_levels.742538619 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:04 AM UTC 24 257176690 ps
T3249 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/61.usbdev_fifo_levels.475640403 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:04 AM UTC 24 254587778 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/62.usbdev_fifo_levels.1453934387 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:04 AM UTC 24 262205935 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/63.usbdev_fifo_levels.3211234806 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 269986791 ps
T3250 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/65.usbdev_fifo_levels.3107826398 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 189337680 ps
T522 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/59.usbdev_endpoint_types.1853984913 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 469889251 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/64.usbdev_fifo_levels.3391431392 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 271704329 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/61.usbdev_endpoint_types.2986919826 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 524737926 ps
T3251 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/58.usbdev_tx_rx_disruption.2022651777 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 654001869 ps
T3252 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/66.usbdev_fifo_levels.2325567774 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 315800919 ps
T3253 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/59.usbdev_tx_rx_disruption.975795294 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 609355082 ps
T3254 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/62.usbdev_tx_rx_disruption.2833410334 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 524995898 ps
T3255 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/61.usbdev_tx_rx_disruption.553361903 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 476718804 ps
T491 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/60.usbdev_endpoint_types.3616534989 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 699614164 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/64.usbdev_endpoint_types.767605718 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 493890605 ps
T500 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/57.usbdev_endpoint_types.129080923 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 641772093 ps
T3256 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/66.usbdev_endpoint_types.1289065678 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 202181411 ps
T3257 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/64.usbdev_tx_rx_disruption.1683049675 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 463733230 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/62.usbdev_endpoint_types.3533098836 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 713404207 ps
T495 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/65.usbdev_endpoint_types.2847430955 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 489021030 ps
T3258 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/60.usbdev_tx_rx_disruption.2362956864 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 586233360 ps
T545 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/63.usbdev_endpoint_types.2986564351 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 426396479 ps
T3259 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/66.usbdev_tx_rx_disruption.2640676080 Sep 24 09:35:03 AM UTC 24 Sep 24 09:35:05 AM UTC 24 607301457 ps
T3260 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/63.usbdev_tx_rx_disruption.51326612 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 559664856 ps
T3261 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/65.usbdev_tx_rx_disruption.646742504 Sep 24 09:35:02 AM UTC 24 Sep 24 09:35:05 AM UTC 24 544611276 ps
T3262 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/49.usbdev_low_speed_traffic.2570885042 Sep 24 09:33:47 AM UTC 24 Sep 24 09:35:32 AM UTC 24 4101985928 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/67.usbdev_fifo_levels.3958295589 Sep 24 09:35:47 AM UTC 24 Sep 24 09:35:49 AM UTC 24 266221555 ps
T571 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/67.usbdev_endpoint_types.4160875471 Sep 24 09:35:47 AM UTC 24 Sep 24 09:35:50 AM UTC 24 355782292 ps
T527 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/69.usbdev_endpoint_types.2592765283 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:50 AM UTC 24 287220030 ps
T3263 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/68.usbdev_fifo_levels.2836854356 Sep 24 09:35:47 AM UTC 24 Sep 24 09:35:50 AM UTC 24 277707724 ps
T3264 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/69.usbdev_fifo_levels.661828239 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:50 AM UTC 24 244203101 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/70.usbdev_fifo_levels.3572490532 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:50 AM UTC 24 271400345 ps
T3265 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/71.usbdev_fifo_levels.15007802 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:50 AM UTC 24 184731341 ps
T573 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/72.usbdev_endpoint_types.2530167238 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:50 AM UTC 24 229511556 ps
T520 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/70.usbdev_endpoint_types.4175264904 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:50 AM UTC 24 428861178 ps
T3266 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/67.usbdev_tx_rx_disruption.2661379855 Sep 24 09:35:47 AM UTC 24 Sep 24 09:35:50 AM UTC 24 637439033 ps
T3267 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/81.usbdev_fifo_levels.2475975826 Sep 24 09:36:37 AM UTC 24 Sep 24 09:36:40 AM UTC 24 326818103 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/74.usbdev_fifo_levels.468428492 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:50 AM UTC 24 148658268 ps
T3268 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/71.usbdev_endpoint_types.3565866331 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:50 AM UTC 24 220081571 ps
T3269 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/68.usbdev_tx_rx_disruption.639832027 Sep 24 09:35:47 AM UTC 24 Sep 24 09:35:50 AM UTC 24 623966062 ps
T3270 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/73.usbdev_endpoint_types.1508102444 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:50 AM UTC 24 154719602 ps
T3271 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/73.usbdev_fifo_levels.1908452709 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:50 AM UTC 24 290610941 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/72.usbdev_fifo_levels.4182364620 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:50 AM UTC 24 325667907 ps
T502 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/68.usbdev_endpoint_types.199345695 Sep 24 09:35:47 AM UTC 24 Sep 24 09:35:50 AM UTC 24 477885015 ps
T3272 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/76.usbdev_fifo_levels.2562094010 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:50 AM UTC 24 161550778 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/75.usbdev_fifo_levels.4024756955 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:50 AM UTC 24 271364339 ps
T3273 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/69.usbdev_tx_rx_disruption.3284831584 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:51 AM UTC 24 626725803 ps
T3274 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/87.usbdev_fifo_levels.3604659691 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:40 AM UTC 24 238247599 ps
T3275 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/78.usbdev_fifo_levels.756415549 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:51 AM UTC 24 153283722 ps
T3276 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/71.usbdev_tx_rx_disruption.3298622804 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:51 AM UTC 24 647385381 ps
T3277 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/77.usbdev_fifo_levels.1386309851 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:51 AM UTC 24 150592985 ps
T3278 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/78.usbdev_endpoint_types.2657779893 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:51 AM UTC 24 214563777 ps
T3279 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/70.usbdev_tx_rx_disruption.728907456 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:51 AM UTC 24 563020703 ps
T3280 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/73.usbdev_tx_rx_disruption.3215028152 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:51 AM UTC 24 484000736 ps
T487 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/75.usbdev_endpoint_types.760360388 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:51 AM UTC 24 460954526 ps
T3281 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/72.usbdev_tx_rx_disruption.2158210416 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:51 AM UTC 24 598970127 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/79.usbdev_fifo_levels.3556544935 Sep 24 09:35:49 AM UTC 24 Sep 24 09:35:51 AM UTC 24 297580321 ps
T3282 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/80.usbdev_fifo_levels.2575766851 Sep 24 09:35:49 AM UTC 24 Sep 24 09:35:51 AM UTC 24 249882584 ps
T3283 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/76.usbdev_tx_rx_disruption.1825449492 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:51 AM UTC 24 605096402 ps
T514 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/79.usbdev_endpoint_types.3008464279 Sep 24 09:35:49 AM UTC 24 Sep 24 09:35:51 AM UTC 24 352661219 ps
T532 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/80.usbdev_endpoint_types.1274431523 Sep 24 09:35:49 AM UTC 24 Sep 24 09:35:51 AM UTC 24 368463319 ps
T3284 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/75.usbdev_tx_rx_disruption.3998515902 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:51 AM UTC 24 615279793 ps
T3285 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/74.usbdev_tx_rx_disruption.1560968783 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:51 AM UTC 24 630596373 ps
T3286 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/77.usbdev_endpoint_types.3936728344 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:51 AM UTC 24 664794982 ps
T509 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/74.usbdev_endpoint_types.1222094343 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:51 AM UTC 24 854415723 ps
T3287 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/77.usbdev_tx_rx_disruption.3558936276 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:52 AM UTC 24 605996669 ps
T524 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/76.usbdev_endpoint_types.3136029068 Sep 24 09:35:48 AM UTC 24 Sep 24 09:35:52 AM UTC 24 728439185 ps
T3288 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/79.usbdev_tx_rx_disruption.2378501297 Sep 24 09:35:49 AM UTC 24 Sep 24 09:35:52 AM UTC 24 554007120 ps
T3289 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/78.usbdev_tx_rx_disruption.1696667698 Sep 24 09:35:49 AM UTC 24 Sep 24 09:35:52 AM UTC 24 481197646 ps
T3290 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/80.usbdev_tx_rx_disruption.1544149038 Sep 24 09:35:51 AM UTC 24 Sep 24 09:35:54 AM UTC 24 494056553 ps
T587 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/81.usbdev_endpoint_types.360087483 Sep 24 09:36:37 AM UTC 24 Sep 24 09:36:39 AM UTC 24 183792986 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/82.usbdev_endpoint_types.1396234455 Sep 24 09:36:37 AM UTC 24 Sep 24 09:36:39 AM UTC 24 232398737 ps
T3291 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/83.usbdev_fifo_levels.829385204 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:40 AM UTC 24 257242002 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/86.usbdev_fifo_levels.617174791 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:40 AM UTC 24 171593430 ps
T3292 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/82.usbdev_fifo_levels.3483745455 Sep 24 09:36:37 AM UTC 24 Sep 24 09:36:40 AM UTC 24 266485263 ps
T3293 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/83.usbdev_tx_rx_disruption.3399641425 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:40 AM UTC 24 507641252 ps
T3294 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/82.usbdev_tx_rx_disruption.3661732156 Sep 24 09:36:37 AM UTC 24 Sep 24 09:36:40 AM UTC 24 486508002 ps
T3295 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/88.usbdev_fifo_levels.2270344567 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:40 AM UTC 24 146398866 ps
T3296 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/84.usbdev_tx_rx_disruption.2452831406 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:40 AM UTC 24 565704727 ps
T3297 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/91.usbdev_fifo_levels.144890356 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:40 AM UTC 24 197739082 ps
T3298 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/85.usbdev_fifo_levels.1991117748 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:40 AM UTC 24 272221242 ps
T3299 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/81.usbdev_tx_rx_disruption.3540760508 Sep 24 09:36:37 AM UTC 24 Sep 24 09:36:40 AM UTC 24 516625498 ps
T594 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/88.usbdev_endpoint_types.3922599846 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:40 AM UTC 24 207687628 ps
T3300 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/90.usbdev_fifo_levels.1270334320 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:40 AM UTC 24 273741855 ps
T3301 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/86.usbdev_tx_rx_disruption.727765889 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:40 AM UTC 24 492885596 ps
T584 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/87.usbdev_endpoint_types.3018927204 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:40 AM UTC 24 369951573 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/92.usbdev_endpoint_types.2582932579 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:40 AM UTC 24 240620146 ps
T526 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/84.usbdev_endpoint_types.1034128640 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:40 AM UTC 24 621754067 ps
T506 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/83.usbdev_endpoint_types.1658956084 Sep 24 09:36:37 AM UTC 24 Sep 24 09:36:40 AM UTC 24 598581207 ps
T3302 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/85.usbdev_tx_rx_disruption.1413334332 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:40 AM UTC 24 559511146 ps
T3303 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/89.usbdev_endpoint_types.3871642419 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:41 AM UTC 24 331805348 ps
T568 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/91.usbdev_endpoint_types.1666994947 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:41 AM UTC 24 470755447 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/94.usbdev_fifo_levels.3311547153 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:41 AM UTC 24 244047583 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/92.usbdev_fifo_levels.1890853014 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:41 AM UTC 24 313039137 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/93.usbdev_fifo_levels.3098847698 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:41 AM UTC 24 288774768 ps
T3304 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/90.usbdev_tx_rx_disruption.3973994615 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:41 AM UTC 24 497226005 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/89.usbdev_fifo_levels.3896803464 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:41 AM UTC 24 272264315 ps
T3305 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/87.usbdev_tx_rx_disruption.3836571667 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:41 AM UTC 24 564012833 ps
T3306 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/88.usbdev_tx_rx_disruption.2251265328 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:41 AM UTC 24 483015233 ps
T539 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/86.usbdev_endpoint_types.3586448650 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:41 AM UTC 24 534363434 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/90.usbdev_endpoint_types.3848387640 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:41 AM UTC 24 610804736 ps
T511 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/85.usbdev_endpoint_types.3246339469 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:41 AM UTC 24 671084585 ps
T3307 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/91.usbdev_tx_rx_disruption.752836869 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:41 AM UTC 24 497234231 ps
T542 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/94.usbdev_endpoint_types.1177197251 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:41 AM UTC 24 574261463 ps
T496 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/93.usbdev_endpoint_types.3569737684 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:41 AM UTC 24 589402123 ps
T3308 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/92.usbdev_tx_rx_disruption.42049297 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:41 AM UTC 24 649760885 ps
T3309 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/89.usbdev_tx_rx_disruption.4231011766 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:41 AM UTC 24 565145281 ps
T3310 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/93.usbdev_tx_rx_disruption.2024197196 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:41 AM UTC 24 542836318 ps
T3311 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/94.usbdev_tx_rx_disruption.587147854 Sep 24 09:36:38 AM UTC 24 Sep 24 09:36:41 AM UTC 24 563575215 ps
T3312 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/96.usbdev_fifo_levels.3424970745 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:28 AM UTC 24 152374837 ps
T581 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/98.usbdev_endpoint_types.1278251928 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:28 AM UTC 24 227151195 ps
T3313 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/96.usbdev_endpoint_types.2121586941 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:28 AM UTC 24 163796108 ps
T3314 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/99.usbdev_endpoint_types.2356165862 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:28 AM UTC 24 206201852 ps
T3315 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/95.usbdev_fifo_levels.3711333415 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:28 AM UTC 24 250884327 ps
T3316 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/98.usbdev_fifo_levels.1142441284 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:28 AM UTC 24 152413791 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/97.usbdev_fifo_levels.1538130444 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:29 AM UTC 24 257673535 ps
T3317 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/99.usbdev_fifo_levels.74626234 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:29 AM UTC 24 291419841 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/95.usbdev_endpoint_types.3835222189 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:29 AM UTC 24 421824229 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/101.usbdev_fifo_levels.1092677096 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:29 AM UTC 24 260923882 ps
T553 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/101.usbdev_endpoint_types.1548458056 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:29 AM UTC 24 209421973 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/100.usbdev_fifo_levels.1283452125 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:29 AM UTC 24 290037606 ps
T3318 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/112.usbdev_fifo_levels.1235226896 Sep 24 09:38:16 AM UTC 24 Sep 24 09:38:18 AM UTC 24 149136476 ps
T3319 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/103.usbdev_endpoint_types.4186991178 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:29 AM UTC 24 195972749 ps
T3320 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/95.usbdev_tx_rx_disruption.2146258459 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:29 AM UTC 24 462399594 ps
T3321 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/106.usbdev_tx_rx_disruption.2749896301 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:30 AM UTC 24 556143016 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/110.usbdev_fifo_levels.3956254326 Sep 24 09:38:16 AM UTC 24 Sep 24 09:38:18 AM UTC 24 247427144 ps
T3322 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/96.usbdev_tx_rx_disruption.610676659 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:29 AM UTC 24 493633554 ps
T3323 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/99.usbdev_tx_rx_disruption.2420395145 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:29 AM UTC 24 493283125 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/109.usbdev_fifo_levels.2297079700 Sep 24 09:38:16 AM UTC 24 Sep 24 09:38:18 AM UTC 24 295023370 ps
T3324 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/97.usbdev_tx_rx_disruption.3287337325 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:29 AM UTC 24 631436555 ps
T507 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/97.usbdev_endpoint_types.887062064 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:29 AM UTC 24 609518191 ps
T534 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/100.usbdev_endpoint_types.3684314858 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:29 AM UTC 24 534667360 ps
T583 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/102.usbdev_endpoint_types.2637623813 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:29 AM UTC 24 342427265 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/103.usbdev_fifo_levels.1622122166 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:29 AM UTC 24 266471569 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/98.usbdev_tx_rx_disruption.2439065868 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:29 AM UTC 24 553953670 ps
T3325 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/104.usbdev_fifo_levels.3150140437 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:29 AM UTC 24 166038233 ps
T3326 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/100.usbdev_tx_rx_disruption.3284552217 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:29 AM UTC 24 446988383 ps
T582 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/104.usbdev_endpoint_types.3629953087 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:29 AM UTC 24 278994873 ps
T3327 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/101.usbdev_tx_rx_disruption.3806948935 Sep 24 09:37:26 AM UTC 24 Sep 24 09:37:29 AM UTC 24 526657953 ps
T503 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/106.usbdev_endpoint_types.1436359292 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:29 AM UTC 24 286827504 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/102.usbdev_fifo_levels.3340742337 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:29 AM UTC 24 321942790 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/105.usbdev_fifo_levels.201846502 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:29 AM UTC 24 275838166 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/106.usbdev_fifo_levels.4115535653 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:30 AM UTC 24 254544956 ps
T3328 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/107.usbdev_fifo_levels.598004566 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:30 AM UTC 24 269639244 ps
T3329 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/108.usbdev_fifo_levels.2991804695 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:30 AM UTC 24 333878683 ps
T3330 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/102.usbdev_tx_rx_disruption.568797334 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:30 AM UTC 24 525004687 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/105.usbdev_endpoint_types.4252568499 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:30 AM UTC 24 559750527 ps
T3331 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/104.usbdev_tx_rx_disruption.1457362442 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:30 AM UTC 24 590595670 ps
T3332 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/107.usbdev_tx_rx_disruption.1702922878 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:30 AM UTC 24 462349532 ps
T530 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/107.usbdev_endpoint_types.1235795167 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:30 AM UTC 24 496455298 ps
T3333 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/105.usbdev_tx_rx_disruption.3987535807 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:30 AM UTC 24 505766378 ps
T515 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/108.usbdev_endpoint_types.3933472727 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:30 AM UTC 24 613763863 ps
T3334 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/103.usbdev_tx_rx_disruption.2754125046 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:30 AM UTC 24 570398185 ps
T3335 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/108.usbdev_tx_rx_disruption.2083024761 Sep 24 09:37:27 AM UTC 24 Sep 24 09:37:30 AM UTC 24 627513521 ps
T3336 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/110.usbdev_tx_rx_disruption.3519113237 Sep 24 09:38:16 AM UTC 24 Sep 24 09:38:18 AM UTC 24 478183864 ps
T3337 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/116.usbdev_fifo_levels.3046460960 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:18 AM UTC 24 148528058 ps
T3338 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/133.usbdev_tx_rx_disruption.1704779371 Sep 24 09:39:09 AM UTC 24 Sep 24 09:39:12 AM UTC 24 562959991 ps
T512 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/135.usbdev_endpoint_types.453680015 Sep 24 09:39:09 AM UTC 24 Sep 24 09:39:12 AM UTC 24 669887639 ps
T3339 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/114.usbdev_endpoint_types.849962955 Sep 24 09:38:16 AM UTC 24 Sep 24 09:38:19 AM UTC 24 286806367 ps
T3340 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/137.usbdev_fifo_levels.2414271643 Sep 24 09:39:57 AM UTC 24 Sep 24 09:39:59 AM UTC 24 268603889 ps
T492 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/109.usbdev_endpoint_types.3252839001 Sep 24 09:38:16 AM UTC 24 Sep 24 09:38:19 AM UTC 24 584857219 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/114.usbdev_fifo_levels.363874574 Sep 24 09:38:16 AM UTC 24 Sep 24 09:38:19 AM UTC 24 257029278 ps
T3341 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/115.usbdev_fifo_levels.1589000020 Sep 24 09:38:16 AM UTC 24 Sep 24 09:38:19 AM UTC 24 153628718 ps
T3342 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/132.usbdev_tx_rx_disruption.3388442220 Sep 24 09:39:09 AM UTC 24 Sep 24 09:39:12 AM UTC 24 717713511 ps
T3343 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/111.usbdev_tx_rx_disruption.2791459822 Sep 24 09:38:16 AM UTC 24 Sep 24 09:38:19 AM UTC 24 467494591 ps
T567 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/113.usbdev_endpoint_types.3160688854 Sep 24 09:38:16 AM UTC 24 Sep 24 09:38:19 AM UTC 24 325178960 ps
T516 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/116.usbdev_endpoint_types.199025315 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:19 AM UTC 24 365023619 ps
T3344 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/139.usbdev_fifo_levels.469293364 Sep 24 09:39:57 AM UTC 24 Sep 24 09:39:59 AM UTC 24 160171958 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/117.usbdev_fifo_levels.581257136 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:19 AM UTC 24 259754482 ps
T3345 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/109.usbdev_tx_rx_disruption.2899404266 Sep 24 09:38:16 AM UTC 24 Sep 24 09:38:19 AM UTC 24 541564886 ps
T3346 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/117.usbdev_endpoint_types.3630291038 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:19 AM UTC 24 237772751 ps
T3347 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/119.usbdev_endpoint_types.79022292 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:19 AM UTC 24 175354835 ps
T3348 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/120.usbdev_fifo_levels.504329310 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:19 AM UTC 24 264434869 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/121.usbdev_fifo_levels.2791012050 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:19 AM UTC 24 185742572 ps
T3349 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/119.usbdev_fifo_levels.4272923363 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:19 AM UTC 24 182804043 ps
T3350 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/115.usbdev_tx_rx_disruption.3950169901 Sep 24 09:38:16 AM UTC 24 Sep 24 09:38:19 AM UTC 24 455464528 ps
T556 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/120.usbdev_endpoint_types.1509144642 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:19 AM UTC 24 240340625 ps
T3351 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/118.usbdev_fifo_levels.2666554842 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:19 AM UTC 24 279423771 ps
T3352 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/116.usbdev_tx_rx_disruption.1377411368 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:19 AM UTC 24 452365578 ps
T3353 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/113.usbdev_tx_rx_disruption.3283665389 Sep 24 09:38:16 AM UTC 24 Sep 24 09:38:19 AM UTC 24 593520145 ps
T3354 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/112.usbdev_tx_rx_disruption.1727553625 Sep 24 09:38:16 AM UTC 24 Sep 24 09:38:19 AM UTC 24 509164122 ps
T577 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/118.usbdev_endpoint_types.1450451801 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:19 AM UTC 24 444989497 ps
T3355 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/114.usbdev_tx_rx_disruption.30325397 Sep 24 09:38:16 AM UTC 24 Sep 24 09:38:19 AM UTC 24 460105767 ps
T517 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/111.usbdev_endpoint_types.1138720865 Sep 24 09:38:16 AM UTC 24 Sep 24 09:38:19 AM UTC 24 899057047 ps
T3356 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/118.usbdev_tx_rx_disruption.2503684084 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:19 AM UTC 24 470837069 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/122.usbdev_fifo_levels.1734483287 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:19 AM UTC 24 274029103 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/115.usbdev_endpoint_types.1435309988 Sep 24 09:38:16 AM UTC 24 Sep 24 09:38:19 AM UTC 24 748254562 ps
T3357 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/117.usbdev_tx_rx_disruption.1037212968 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:19 AM UTC 24 644264475 ps
T508 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/121.usbdev_endpoint_types.1270501472 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:20 AM UTC 24 522512416 ps
T531 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/122.usbdev_endpoint_types.561168847 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:20 AM UTC 24 427749677 ps
T3358 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/121.usbdev_tx_rx_disruption.3289675449 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:20 AM UTC 24 446883599 ps
T3359 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/122.usbdev_tx_rx_disruption.163013522 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:20 AM UTC 24 527783893 ps
T3360 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/119.usbdev_tx_rx_disruption.1337886868 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:20 AM UTC 24 582291433 ps
T3361 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/120.usbdev_tx_rx_disruption.935906247 Sep 24 09:38:17 AM UTC 24 Sep 24 09:38:20 AM UTC 24 660968866 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/123.usbdev_fifo_levels.717878475 Sep 24 09:39:07 AM UTC 24 Sep 24 09:39:09 AM UTC 24 184676920 ps
T595 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/124.usbdev_endpoint_types.1985027419 Sep 24 09:39:07 AM UTC 24 Sep 24 09:39:09 AM UTC 24 198851604 ps
T488 /workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/coverage/default/123.usbdev_endpoint_types.3619986907 Sep 24 09:39:07 AM UTC 24 Sep 24 09:39:09 AM UTC 24 251606431 ps
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