Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.49 88.61 85.76 70.93 86.47 88.35 98.80


Total test records in report: 1927
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T293 /workspace/coverage/cover_reg_top/24.xbar_access_same_device.3859169718 Dec 31 01:37:16 PM PST 23 Dec 31 01:38:11 PM PST 23 578997515 ps
T142 /workspace/coverage/cover_reg_top/42.xbar_smoke.828537536 Dec 31 01:39:16 PM PST 23 Dec 31 01:39:23 PM PST 23 47768842 ps
T177 /workspace/coverage/cover_reg_top/0.xbar_same_source.833384136 Dec 31 01:34:50 PM PST 23 Dec 31 01:35:25 PM PST 23 382821457 ps
T305 /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.229310405 Dec 31 01:43:13 PM PST 23 Dec 31 01:45:31 PM PST 23 3346695745 ps
T443 /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2146468601 Dec 31 01:36:07 PM PST 23 Dec 31 01:36:22 PM PST 23 111177512 ps
T257 /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.2391090483 Dec 31 01:37:40 PM PST 23 Dec 31 01:37:58 PM PST 23 155845344 ps
T156 /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.3365440914 Dec 31 01:34:59 PM PST 23 Dec 31 01:35:52 PM PST 23 1199054108 ps
T120 /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.949782752 Dec 31 01:41:57 PM PST 23 Dec 31 01:51:58 PM PST 23 56068101581 ps
T444 /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.3764064570 Dec 31 01:43:36 PM PST 23 Dec 31 01:44:54 PM PST 23 4680371905 ps
T445 /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.2395945157 Dec 31 01:39:38 PM PST 23 Dec 31 01:39:51 PM PST 23 47408245 ps
T446 /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.3729473737 Dec 31 01:39:48 PM PST 23 Dec 31 01:39:55 PM PST 23 44295638 ps
T147 /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.2602484238 Dec 31 01:41:53 PM PST 23 Dec 31 01:42:22 PM PST 23 297755811 ps
T447 /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.4141370093 Dec 31 01:44:41 PM PST 23 Dec 31 01:46:19 PM PST 23 5883799473 ps
T448 /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.445033344 Dec 31 01:43:08 PM PST 23 Dec 31 01:43:17 PM PST 23 50734821 ps
T449 /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.2122889162 Dec 31 01:37:19 PM PST 23 Dec 31 01:37:33 PM PST 23 135114761 ps
T450 /workspace/coverage/cover_reg_top/77.xbar_stress_all.3687629937 Dec 31 01:43:13 PM PST 23 Dec 31 01:43:18 PM PST 23 5817075 ps
T300 /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.2921331219 Dec 31 01:44:22 PM PST 23 Dec 31 02:00:38 PM PST 23 60214102910 ps
T118 /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.3313691469 Dec 31 01:40:16 PM PST 23 Dec 31 01:40:46 PM PST 23 297931566 ps
T130 /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.736372794 Dec 31 01:45:19 PM PST 23 Dec 31 01:49:30 PM PST 23 1490314573 ps
T451 /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.3583139726 Dec 31 01:42:53 PM PST 23 Dec 31 01:43:02 PM PST 23 36386940 ps
T341 /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.3387783595 Dec 31 01:40:03 PM PST 23 Dec 31 01:45:25 PM PST 23 5307747766 ps
T311 /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3962364686 Dec 31 01:36:32 PM PST 23 Dec 31 01:46:28 PM PST 23 33864453880 ps
T213 /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.2062479691 Dec 31 01:39:34 PM PST 23 Dec 31 01:48:20 PM PST 23 31926187293 ps
T274 /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.842263595 Dec 31 01:41:56 PM PST 23 Dec 31 01:42:10 PM PST 23 130510733 ps
T267 /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.502792488 Dec 31 01:39:19 PM PST 23 Dec 31 01:49:59 PM PST 23 14773862526 ps
T452 /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.78026638 Dec 31 01:34:16 PM PST 23 Dec 31 01:35:52 PM PST 23 5657111797 ps
T301 /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3417542547 Dec 31 01:35:09 PM PST 23 Dec 31 01:46:57 PM PST 23 41594313696 ps
T453 /workspace/coverage/cover_reg_top/27.xbar_access_same_device.785253711 Dec 31 01:37:43 PM PST 23 Dec 31 01:38:44 PM PST 23 1589435802 ps
T294 /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.164303478 Dec 31 01:40:05 PM PST 23 Dec 31 01:55:44 PM PST 23 56140372923 ps
T40 /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.3298932250 Dec 31 01:34:27 PM PST 23 Dec 31 01:40:40 PM PST 23 10699968570 ps
T454 /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1804044655 Dec 31 01:37:43 PM PST 23 Dec 31 01:37:51 PM PST 23 54517979 ps
T186 /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.859278686 Dec 31 01:43:05 PM PST 23 Dec 31 01:43:29 PM PST 23 253891338 ps
T173 /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.2294113438 Dec 31 01:37:22 PM PST 23 Dec 31 01:38:51 PM PST 23 5282847033 ps
T455 /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.462565112 Dec 31 01:43:33 PM PST 23 Dec 31 01:43:41 PM PST 23 49328312 ps
T456 /workspace/coverage/cover_reg_top/64.xbar_error_random.1711087811 Dec 31 01:41:54 PM PST 23 Dec 31 01:43:12 PM PST 23 2232653124 ps
T33 /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.322326015 Dec 31 01:36:41 PM PST 23 Dec 31 02:06:39 PM PST 23 15796160500 ps
T263 /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.605306173 Dec 31 01:42:23 PM PST 23 Dec 31 01:46:09 PM PST 23 22802943243 ps
T131 /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.1454064723 Dec 31 01:37:49 PM PST 23 Dec 31 01:53:21 PM PST 23 53858279410 ps
T39 /workspace/coverage/cover_reg_top/7.chip_csr_rw.1794543354 Dec 31 01:35:00 PM PST 23 Dec 31 01:44:55 PM PST 23 5575900072 ps
T148 /workspace/coverage/cover_reg_top/1.xbar_random.1626803736 Dec 31 01:35:04 PM PST 23 Dec 31 01:35:46 PM PST 23 451447396 ps
T457 /workspace/coverage/cover_reg_top/25.xbar_smoke.2825062024 Dec 31 01:37:18 PM PST 23 Dec 31 01:37:30 PM PST 23 55529816 ps
T458 /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.216234097 Dec 31 01:42:36 PM PST 23 Dec 31 01:42:47 PM PST 23 45929504 ps
T194 /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2979067551 Dec 31 01:41:55 PM PST 23 Dec 31 01:47:11 PM PST 23 2730908954 ps
T459 /workspace/coverage/cover_reg_top/88.xbar_error_random.865254971 Dec 31 01:44:13 PM PST 23 Dec 31 01:44:27 PM PST 23 103204959 ps
T238 /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.902616138 Dec 31 01:43:32 PM PST 23 Dec 31 01:44:51 PM PST 23 4637498664 ps
T460 /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.2583193516 Dec 31 01:41:24 PM PST 23 Dec 31 01:41:42 PM PST 23 159885389 ps
T461 /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.3455613190 Dec 31 01:45:02 PM PST 23 Dec 31 01:46:47 PM PST 23 5597165075 ps
T462 /workspace/coverage/cover_reg_top/10.xbar_smoke.962430153 Dec 31 01:35:25 PM PST 23 Dec 31 01:35:32 PM PST 23 42396837 ps
T463 /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1288072999 Dec 31 01:34:51 PM PST 23 Dec 31 01:36:47 PM PST 23 9608987630 ps
T329 /workspace/coverage/cover_reg_top/83.xbar_access_same_device.3448863427 Dec 31 01:43:11 PM PST 23 Dec 31 01:43:30 PM PST 23 194657156 ps
T464 /workspace/coverage/cover_reg_top/94.xbar_error_random.2382529240 Dec 31 01:45:18 PM PST 23 Dec 31 01:45:34 PM PST 23 116277307 ps
T174 /workspace/coverage/cover_reg_top/14.xbar_stress_all.2887022029 Dec 31 01:35:46 PM PST 23 Dec 31 01:40:26 PM PST 23 7946852128 ps
T334 /workspace/coverage/cover_reg_top/70.xbar_access_same_device.4284736678 Dec 31 01:43:09 PM PST 23 Dec 31 01:43:31 PM PST 23 498567787 ps
T465 /workspace/coverage/cover_reg_top/24.xbar_error_random.2433756314 Dec 31 01:37:17 PM PST 23 Dec 31 01:37:54 PM PST 23 911415980 ps
T466 /workspace/coverage/cover_reg_top/74.xbar_error_random.3484909044 Dec 31 01:42:49 PM PST 23 Dec 31 01:43:40 PM PST 23 614890026 ps
T249 /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.1357530408 Dec 31 01:40:12 PM PST 23 Dec 31 01:55:03 PM PST 23 54609547907 ps
T467 /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.3648660882 Dec 31 01:44:10 PM PST 23 Dec 31 01:45:14 PM PST 23 3688032154 ps
T468 /workspace/coverage/cover_reg_top/9.xbar_smoke.3395245819 Dec 31 01:35:09 PM PST 23 Dec 31 01:35:16 PM PST 23 53986794 ps
T211 /workspace/coverage/cover_reg_top/10.chip_tl_errors.3028015458 Dec 31 01:35:57 PM PST 23 Dec 31 01:40:04 PM PST 23 3517538204 ps
T469 /workspace/coverage/cover_reg_top/36.xbar_random.2188962984 Dec 31 01:38:22 PM PST 23 Dec 31 01:38:40 PM PST 23 435260179 ps
T190 /workspace/coverage/cover_reg_top/61.xbar_random.882025257 Dec 31 01:41:22 PM PST 23 Dec 31 01:42:02 PM PST 23 1049335130 ps
T470 /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3207104899 Dec 31 01:35:37 PM PST 23 Dec 31 01:36:41 PM PST 23 3972752769 ps
T471 /workspace/coverage/cover_reg_top/42.xbar_random.402570948 Dec 31 01:39:36 PM PST 23 Dec 31 01:39:47 PM PST 23 113627180 ps
T295 /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.669496944 Dec 31 01:42:00 PM PST 23 Dec 31 02:04:41 PM PST 23 81762733727 ps
T125 /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.939629584 Dec 31 01:40:07 PM PST 23 Dec 31 01:55:32 PM PST 23 90421393573 ps
T135 /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.4098289674 Dec 31 01:42:56 PM PST 23 Dec 31 02:12:38 PM PST 23 110593876296 ps
T472 /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.3944936764 Dec 31 01:42:48 PM PST 23 Dec 31 01:43:21 PM PST 23 716812999 ps
T473 /workspace/coverage/cover_reg_top/80.xbar_random.994829715 Dec 31 01:42:49 PM PST 23 Dec 31 01:43:32 PM PST 23 1021688735 ps
T214 /workspace/coverage/cover_reg_top/16.chip_tl_errors.4047853321 Dec 31 01:37:14 PM PST 23 Dec 31 01:42:57 PM PST 23 4874786819 ps
T474 /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.1307594197 Dec 31 01:34:51 PM PST 23 Dec 31 01:38:04 PM PST 23 20145148770 ps
T475 /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.4096734565 Dec 31 01:40:19 PM PST 23 Dec 31 01:40:51 PM PST 23 678175698 ps
T476 /workspace/coverage/cover_reg_top/91.xbar_smoke.818279524 Dec 31 01:44:16 PM PST 23 Dec 31 01:44:24 PM PST 23 49495582 ps
T477 /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.1825626925 Dec 31 01:39:14 PM PST 23 Dec 31 01:39:22 PM PST 23 44451746 ps
T478 /workspace/coverage/cover_reg_top/98.xbar_same_source.3771816373 Dec 31 01:44:39 PM PST 23 Dec 31 01:45:39 PM PST 23 2144016102 ps
T479 /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.3394435441 Dec 31 01:40:06 PM PST 23 Dec 31 01:41:22 PM PST 23 7343049888 ps
T480 /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.413091921 Dec 31 01:39:16 PM PST 23 Dec 31 01:39:49 PM PST 23 776497696 ps
T182 /workspace/coverage/cover_reg_top/24.xbar_random.2012583084 Dec 31 01:37:22 PM PST 23 Dec 31 01:37:53 PM PST 23 662721236 ps
T481 /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.4202553424 Dec 31 01:37:21 PM PST 23 Dec 31 01:37:35 PM PST 23 66858686 ps
T482 /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2754639802 Dec 31 01:35:07 PM PST 23 Dec 31 01:35:14 PM PST 23 49698584 ps
T215 /workspace/coverage/cover_reg_top/3.chip_tl_errors.2349852805 Dec 31 01:34:14 PM PST 23 Dec 31 01:41:02 PM PST 23 4777154146 ps
T483 /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.585619023 Dec 31 01:40:16 PM PST 23 Dec 31 01:41:31 PM PST 23 4244349214 ps
T307 /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3558504068 Dec 31 01:36:28 PM PST 23 Dec 31 02:01:46 PM PST 23 88832738876 ps
T169 /workspace/coverage/cover_reg_top/2.xbar_same_source.3388290499 Dec 31 01:33:55 PM PST 23 Dec 31 01:34:39 PM PST 23 485148007 ps
T484 /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3286390396 Dec 31 01:36:08 PM PST 23 Dec 31 01:37:52 PM PST 23 6372362618 ps
T485 /workspace/coverage/cover_reg_top/86.xbar_access_same_device.2165427996 Dec 31 01:44:00 PM PST 23 Dec 31 01:45:12 PM PST 23 765055856 ps
T127 /workspace/coverage/cover_reg_top/23.xbar_same_source.2305953080 Dec 31 01:37:19 PM PST 23 Dec 31 01:38:32 PM PST 23 2583211083 ps
T486 /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.2781340636 Dec 31 01:44:16 PM PST 23 Dec 31 01:51:42 PM PST 23 3310558312 ps
T312 /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.502799024 Dec 31 01:35:29 PM PST 23 Dec 31 02:11:02 PM PST 23 122196085903 ps
T487 /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.3896928158 Dec 31 01:42:48 PM PST 23 Dec 31 01:42:59 PM PST 23 52162386 ps
T488 /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.2224077000 Dec 31 01:44:42 PM PST 23 Dec 31 01:44:49 PM PST 23 38891138 ps
T489 /workspace/coverage/cover_reg_top/27.xbar_same_source.429173721 Dec 31 01:38:21 PM PST 23 Dec 31 01:39:13 PM PST 23 1609054075 ps
T255 /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.933604407 Dec 31 01:40:27 PM PST 23 Dec 31 01:41:00 PM PST 23 241108103 ps
T490 /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.396626334 Dec 31 01:36:51 PM PST 23 Dec 31 01:37:24 PM PST 23 254006417 ps
T216 /workspace/coverage/cover_reg_top/75.xbar_stress_all.1900289263 Dec 31 01:42:53 PM PST 23 Dec 31 01:44:06 PM PST 23 2213214552 ps
T491 /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.8165394 Dec 31 01:44:40 PM PST 23 Dec 31 01:45:06 PM PST 23 556662457 ps
T492 /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.3286885926 Dec 31 01:40:47 PM PST 23 Dec 31 01:41:13 PM PST 23 226473428 ps
T493 /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.1520084790 Dec 31 01:35:01 PM PST 23 Dec 31 01:38:44 PM PST 23 5071499630 ps
T351 /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.283578688 Dec 31 01:43:27 PM PST 23 Dec 31 01:47:08 PM PST 23 565324600 ps
T262 /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.220041943 Dec 31 01:35:13 PM PST 23 Dec 31 01:49:08 PM PST 23 79162404398 ps
T494 /workspace/coverage/cover_reg_top/39.xbar_smoke.3633008844 Dec 31 01:39:34 PM PST 23 Dec 31 01:39:48 PM PST 23 172198354 ps
T495 /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.260255331 Dec 31 01:35:05 PM PST 23 Dec 31 01:36:37 PM PST 23 8130918620 ps
T314 /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.1663979003 Dec 31 01:38:24 PM PST 23 Dec 31 01:40:12 PM PST 23 2303833293 ps
T496 /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.1384253390 Dec 31 01:43:35 PM PST 23 Dec 31 01:43:43 PM PST 23 45451121 ps
T28 /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.3604645845 Dec 31 01:35:07 PM PST 23 Dec 31 01:38:27 PM PST 23 4323689500 ps
T497 /workspace/coverage/cover_reg_top/80.xbar_error_random.3961752885 Dec 31 01:42:48 PM PST 23 Dec 31 01:43:15 PM PST 23 519131939 ps
T498 /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3392015095 Dec 31 01:36:06 PM PST 23 Dec 31 01:36:32 PM PST 23 218919346 ps
T179 /workspace/coverage/cover_reg_top/78.xbar_same_source.2137869611 Dec 31 01:43:12 PM PST 23 Dec 31 01:44:09 PM PST 23 1857163940 ps
T499 /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.966848993 Dec 31 01:37:50 PM PST 23 Dec 31 01:38:00 PM PST 23 46091285 ps
T500 /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3808533674 Dec 31 01:36:38 PM PST 23 Dec 31 01:44:57 PM PST 23 13170938527 ps
T151 /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.570738203 Dec 31 01:39:17 PM PST 23 Dec 31 01:39:53 PM PST 23 294727472 ps
T501 /workspace/coverage/cover_reg_top/59.xbar_smoke.1709055438 Dec 31 01:40:59 PM PST 23 Dec 31 01:41:08 PM PST 23 170224623 ps
T502 /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2865711982 Dec 31 01:35:23 PM PST 23 Dec 31 01:36:52 PM PST 23 4965638273 ps
T503 /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.2055903900 Dec 31 01:41:20 PM PST 23 Dec 31 01:41:43 PM PST 23 670361982 ps
T158 /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.880349974 Dec 31 01:42:56 PM PST 23 Dec 31 01:43:43 PM PST 23 504831098 ps
T121 /workspace/coverage/cover_reg_top/1.xbar_same_source.822634118 Dec 31 01:34:13 PM PST 23 Dec 31 01:35:26 PM PST 23 2428561839 ps
T327 /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.894282628 Dec 31 01:36:57 PM PST 23 Dec 31 01:47:05 PM PST 23 33947669641 ps
T175 /workspace/coverage/cover_reg_top/59.xbar_access_same_device.2504869236 Dec 31 01:41:16 PM PST 23 Dec 31 01:42:19 PM PST 23 1675402792 ps
T504 /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.140972391 Dec 31 01:45:00 PM PST 23 Dec 31 01:46:11 PM PST 23 726579787 ps
T505 /workspace/coverage/cover_reg_top/68.xbar_smoke.4103903594 Dec 31 01:41:58 PM PST 23 Dec 31 01:42:05 PM PST 23 46927229 ps
T506 /workspace/coverage/cover_reg_top/75.xbar_random.77855791 Dec 31 01:42:31 PM PST 23 Dec 31 01:44:14 PM PST 23 2344581308 ps
T507 /workspace/coverage/cover_reg_top/55.xbar_smoke.3187648029 Dec 31 01:40:45 PM PST 23 Dec 31 01:40:52 PM PST 23 50487813 ps
T508 /workspace/coverage/cover_reg_top/40.xbar_access_same_device.1107490680 Dec 31 01:39:38 PM PST 23 Dec 31 01:40:08 PM PST 23 309680250 ps
T509 /workspace/coverage/cover_reg_top/63.xbar_smoke.78723347 Dec 31 01:41:59 PM PST 23 Dec 31 01:42:09 PM PST 23 162925895 ps
T510 /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.788790224 Dec 31 01:37:12 PM PST 23 Dec 31 01:38:57 PM PST 23 9073451522 ps
T511 /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2141664259 Dec 31 01:34:29 PM PST 23 Dec 31 01:35:19 PM PST 23 2726984701 ps
T30 /workspace/coverage/cover_reg_top/17.chip_csr_rw.2101760340 Dec 31 01:37:05 PM PST 23 Dec 31 01:48:04 PM PST 23 6331980980 ps
T45 /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.1876976158 Dec 31 01:34:34 PM PST 23 Dec 31 02:02:21 PM PST 23 15844052840 ps
T512 /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.3483529005 Dec 31 01:41:39 PM PST 23 Dec 31 01:48:53 PM PST 23 38649000369 ps
T513 /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.2604910101 Dec 31 01:42:45 PM PST 23 Dec 31 01:45:24 PM PST 23 2188827242 ps
T514 /workspace/coverage/cover_reg_top/56.xbar_error_random.3097498764 Dec 31 01:40:54 PM PST 23 Dec 31 01:41:37 PM PST 23 1383100683 ps
T162 /workspace/coverage/cover_reg_top/33.xbar_random.1772640192 Dec 31 01:39:10 PM PST 23 Dec 31 01:39:31 PM PST 23 196426159 ps
T265 /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.1160134653 Dec 31 01:40:00 PM PST 23 Dec 31 01:45:08 PM PST 23 28416429716 ps
T515 /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.2884188708 Dec 31 01:42:47 PM PST 23 Dec 31 01:43:28 PM PST 23 954086127 ps
T516 /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1845225494 Dec 31 01:36:32 PM PST 23 Dec 31 01:36:42 PM PST 23 145936303 ps
T517 /workspace/coverage/cover_reg_top/49.xbar_access_same_device.3474496449 Dec 31 01:40:27 PM PST 23 Dec 31 01:41:04 PM PST 23 370990847 ps
T518 /workspace/coverage/cover_reg_top/54.xbar_same_source.776557036 Dec 31 01:40:47 PM PST 23 Dec 31 01:41:06 PM PST 23 501567018 ps
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